MT28C6428P20FM-80 TET Micron Technology Inc, MT28C6428P20FM-80 TET Datasheet - Page 27

• Manufacturer Part Number: MT28C6428P20FM-80 TET
• Manufacturer: Micron Technology Inc

Specifications of MT28C6428P20FM-80 TET

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

READ-WHILE-WRITE/ERASE
CONCURRENCY
while erasing/writing to another bank. Once a bank
enters the WRITE/ERASE operation, the other bank
automatically enters read array mode. For example,
during a READ CONCURRENCY operation, if a PRO-
GRAM/ERASE command is issued in bank a, then bank
a changes to the read status mode and bank b defaults
to the read array mode. The device reads from bank b if
the latched address resides in bank b (see Figure 10).
Similarly, if a PROGRAM/ERASE command is issued in
bank b, then bank b changes to read status mode and
bank a defaults to read array mode. When returning to
bank a, the device reads program/erase status if the
latched address resides in bank a.
status register after returning from concurrent read in
the other bank.
ter, concurrent operation is not allowed on the top boot
device. Concurrent READ of the CFI or the chip protec-
tion register is only allowed when a PROGRAM or ERASE
operation is performed on bank b on the bottom boot
device. For a bottom boot device, reading of the CFI
table or the chip protection register is only allowed if
bank b is in read array mode. For a top boot device,
reading of the CFI table or the chip protection register
is only allowed if bank a is in read array mode.
BLOCK LOCKING
MT28C6428P18 devices provide a flexible locking
scheme which allows each block to be individually
locked or unlocked with no latency.
The first level allows software-only control of block lock-
ing (for data which needs to be changed frequently),
while the second level requires hardware interaction
before locking can be changed (code which does not
require frequent updates).
state of a block; for example, state [001] means
F_WP# = 0, DQ0 = 0 and DQ1 = 1.
NOTE: All blocks are software-locked upon comple-
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02
It is possible for the device to read from one bank
A correct bank address must be specified to read
When reading the CFI or the chip protection regis-
The Flash memory of the MT28C6428P20 and
The devices offer two-level protection for the blocks.
Control signals F_WP#, DQ0, and DQ1 define the
Table 9 defines all of the possible locking states.
tion of the power-up sequence.
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
27
512K x 16 SRAM COMBO MEMORY
LOCKED STATE
reset sequence, all blocks are locked (states [001] or
[101]). This means full protection from alteration. Any
PROGRAM or ERASE operations attempted on a locked
block will return an error on bit SR1 of the status regis-
ter. The status of a locked block can be changed to
unlocked or lock down using the appropriate software
commands. Writing the lock command sequence, 60h
followed by 01h, can lock an unlocked block.
UNLOCKED STATE
programmed or erased. All unlocked blocks return to
the locked state when the device is reset or powered
down. An unlocked block can be locked or locked down
using the appropriate software command sequence,
60h followed by D0h. (See Table 4.)
Bank a
1 - Erasing/writing to bank a
2 - Erasing in bank a can be
3 - After the WRITE in that block
1 - Reading bank a
After a power-up sequence completion, or after a
Unlocked blocks (states [000], [100], [110]) can be
suspended, and a WRITE to
another block in bank a
can be initiated.
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
READ-While-WRITE Concurrency
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 10
Bank b
1 - Reading from bank b
1 - Erasing/writing to bank b
2 - Erasing in bank b can be
3 - After the WRITE in that block
suspended, and a WRITE to
another block in bank b
can be initiated.
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
©2002, Micron Technology, Inc.