WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 89

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Table 41. Pulse Shaping Indirect Address Register, PSIAD (10h)
Table 42. Pulse Shaping Data Register, PSDAT (11h) for Intel
Table 43. Output Enable Register, OER - 12h
Table 44. AIS Status Monitor Register, AIS - 13h
Table 45. AIS Interrupt Enable Register, AISIE - 14h
3 - 7
3 - 7
Bit
Bit
0-2
0-2
1. On power-on reset the register is set to “0”.
Bit
7:0
Bit
7:0
Bit
7:0
1
1
LENAD 0-2
AISIE7:0
LEN2-0
AIS7:0
OE7:0
Name
Name
Name
Name
Name
-
-
Output Enable.
Alarm Indication Signal Status Monitor.
Alarm Indication Signal Interrupt Enable.
• On power-up, all OE7:0 bits are cleared to ‘0’.
• When an OE bit is set to ‘1’, the output driver of its corresponding
• On power-up, all AIS7:0 bits are cleared to ‘0’.
• All AIS interrupts are cleared by a single read operation.
• Each time a channel receiver detects an AIS condition, its corresponding
• On power-up, all AISIE7:0 bits are cleared to ‘0’.
• When an AISIE bit is set to ‘1’, it enables an AIS interrupt for its
The three bit value written to these bits determine the channel to be addressed. Data
can be read from (written to) the Pulse Shaping Data Register (PSDAT).
LENAD 0-2
Reserved.
Set to 000.
Reserved.
0h
1h
2h
3h
transmitter goes into a high-impedance tristate.
AIS bit is set to ‘1’.
corresponding receiver.
Channel
0
1
2
3
Intel
®
LXT385 Octal E1 S/H PCM Transceiver with JA
Description
Description
Description
LENAD 0-2
Function
Function
4h
5h
6h
7h
®
LXT385 Transceiver
Channel
4
5
6
7
R/W
R/W
R/W
R/W
R/W
R
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