WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 43

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.5
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Table 11. Clocks and Clock-Related Signals (Sheet 1 of 2)
Note: Within this table, ‘RCLK’ references RCLK7:0 and ‘TCLK’ references TCLK7:0. Each RCLK
Clocks and Clock-Related Signals
Table 11
and TCLK signal is used with corresponding signals.
CLKE
•
•
1. DI: Digital Input
Signal
Name
Example: RCLK6 is the receive clock used by RPOS6 and RNEG6.
Example: TCLK5 is the transmit clock used by TPOS5 and TNEG5.
lists and describes LXT385 ransceiver clocks and clock-related signals.
QFP
Pin
115
PBGA
Ball
E13
Signal
Type
DI
Clock Edge Select Input.
CLKE is used in clock and data recovery. When the recovery mode is
for:
• Clock recovery (see
• Data recovery (see
the CLKE pin:
• Low causes (1) both RPOS and RNEG to be valid on the rising
• High causes (1) both RPOS and RNEG to be valid on the falling
Mode”), the output polarity on both RPOS and RNEG is:
• Active-low when CLKE is low.
• Active-high when CLKE is high
edge of RCLK and (2) SDO to be valid on the falling edge of
SCLK. (See
Transceiver - Transmit
edge of RCLK and (2) SDO to be valid on the rising edge of
SCLK. (See
Transceiver - Transmit
Intel
CLKE
High
Low
®
LXT385 Octal E1 S/H PCM Transceiver with JA
RCLK for Valid
RCLK
RCLK
Figure 20
Figure 20
RNEG/RPOS
Section 6.3.4, “Receiver Data Recovery
Section 6.3.1, “Receiver
Signal Description
in
in
Timing”.)
Timing”.)
Section 19, “Intel® LXT385
Section 19, “Intel® LXT385
SCLK for Valid
SCLK
SCLK
SDO
Clocking”), setting
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