WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 100
WJLXT385LE.B1
Manufacturer Part Number
WJLXT385LE.B1
Description
Manufacturer
Cortina Systems Inc
Datasheet
1.WJLXT385LE.B1.pdf
(138 pages)
Specifications of WJLXT385LE.B1
Lead Free Status / RoHS Status
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Intel
Table 51. Instruction Register (IR)
Table 52. JTAG Timing Characteristics
Figure 18. JTAG Timing
®
LXT385 Octal E1 S/H PCM Transceiver with JA
Instruction Register (IR)
The IR is a 3 bit shift register that loads the instruction to be performed. The instructions are shifted
LSB first.
Cycle time
J-TMS/J-TDI to J-TCK rising edge time
J-CLK rising to J-TMS/L-TDI hold time
J-TCLK falling to J-TDO valid
SAMPLE / PRELOAD
TMS
TDO
INTEST_ANALOG
TCK
TDI
Instruction
EXTEST
IDCODE
BYPASS
Table 51
Parameter
shows the valid instruction codes and the corresponding instruction description.
Code #
000
010
100
110
111
Connects the BSR to TDI and TDO. Input pins values are loaded into the
BSR. Output pins values are loaded from the BSR.
Connects the ASR to TDI and TDO. Allows voltage forcing/sensing through
AT1 and AT2. Refer to
Connects the BSR to TDI and TDO. The normal path between the
LXT385ransceiver logic and the I/O pins is maintained. The BSR is loaded
with the signals in the I/O pins.
Connects the IDR to the TDO pin.
Serial data from the TDI input is passed to the TDO output through the 1 bit
Bypass Register.
tSUR
tHT
Tdod
Sym
Tcyc
Tsut
Tht
Min. Typ
200
Table
50
50
tCYC
-
tDOD
49.
-
-
-
-
Comments
Max
50
-
-
-
Unit
ns
ns
ns
ns
Revision Date: 19-Jan-2006
Document Number: 249252
Test Conditions
Revision Number: 006
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