WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 55

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.3.4
6.3.5
6.3.6
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Receiver Data Recovery Mode
In data-recovery mode, the combined analog/digital LOS detector circuit uses only its LOS analog
part, which complies with the ITU-G.775 recommendation. The LOS digital timing is derived from
an internal self-timed circuit. RPOS/RNEG stay active during the loss of signal.
The LXT385 ransceiver monitors the incoming signal amplitude. Typically, any signal below
200mV for more than 30μs asserts the corresponding LOS pin. The LOS condition clears when the
signal amplitude rises above 250mV. To declare an LOS condition in accordance to ITU G.775, the
LXT385 ransceiver requires periods that are more than 10 bits and less than 255 bits.
Receiver Alarm Indication Signal (AIS) Detection
The receiver performs an Alarm Indication Signal (AIS) detection independently of any loopback
mode. This feature is available only in the Host Processor mode and only in the clock-recovery
mode.
Because there is no clock in the data-recovery mode, AIS detection does not work in that mode.
AIS requires MCLK to be active, because the AIS function depends on a clock to count the number
of ones in an interval.
After power-on reset, the LACS register
detection mode or the ETSI 3000 233 detection mode, both of which can be used for AIS. For both
ITU G.775 and ETSI ETS 300 233, the AIS condition is:
Receive Alarm Indication Signal (RAIS) Enable
When an LOS condition is detected, enabling or disabling the Receive Alarm Indication Signal
Enable (RAISEN) bit (bit 6) in the Global Control Register (GCR) affects the setting of the AIS
Status Monitor register.
When an LOS condition is detected and the RAISEN bit setting is:
•
•
•
•
•
•
Declared when in a 512-bit period, the receiver detects less than 3 zeroes in the data stream.
Cleared when in a 512-bit period, the receiver detects 3 or more zeroes in the data stream.
For details on the RAISEN bit, see
page
For details on the AIS Status Monitor register, see
AIS - 13h” on page
‘0’, AIS insertion into the receive path is disabled. In this case, there is no effect on the AIS
Status Monitor register.
‘1’, AIS insertion into the receive path is enabled. In this case, when the signals to the RTIP
and RRING inputs to a receiver are:
— All zeroes, the receiver generates all ones on the RPOS and RNEG outputs, and the AIS
— All ones, the receiver generates all ones on the RPOS and RNEG outputs, and the AIS
Status Monitor register sets to ‘1’.
Status Monitor register clears to ‘0’.
88.
89.
Table 40, “Global Control Register, GCR - 0Fh” on
(Table
Intel
®
38) can be set to select either the ITU G.775
LXT385 Octal E1 S/H PCM Transceiver with JA
Table 44, “AIS Status Monitor Register,
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