LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 41

• Manufacturer Part Number: LAN9312-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NU

• Number Of Primary Switch Ports: 2
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
STRAP NAME
LED_en_strap[7:0]
LED_fun_strap[1:0]
auto_mdix_strap_1
manual_mdix_strap_1
autoneg_strap_1
Table 4.2 Soft-Strap Configuration Strap Definitions
DESCRIPTION
LED Enable Straps: Configures the default value for the
LED_EN bits in the
(LED_CFG). A high value configures the associated
LED/GPIO pin as a LED. A low value configures the
associated LED/GPIO pin as a GPIO.
Note:
LED Function Straps: Configures the default value for the
LED_FUN bits in the
(LED_CFG). When configured low, the corresponding bit
will be cleared. When configured high, the corresponding
bit will be set.
Port 1 Auto-MDIX Enable Strap: Configures the default
value for the Auto-MDIX functionality on Port 1 when the
AMDIXCTL bit in the
Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x)
When configured low, Auto-MDIX is disabled. When
configured high, Auto-MDIX is enabled.
Note:
Port 1 Manual MDIX Strap: Configures MDI(0) or MDIX(1)
for Port 1 when the auto_mdix_strap_1 is low and the
AMDIXCTL bit of the
Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x)
Port 1 Auto Negotiation Enable Strap: Configures the
default value for the
in the PHY_BASIC_CTRL_1 register (See
Section
disabled. When configured high, auto-negotiation is
enabled.
This strap also affects the default value of the following bits:
Refer to the respective register definition sections for
additional information.
PHY_SPEED_SEL_LSB and PHY_DUPLEX bits of the
Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x)
10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex
(bit 5) bits of the
Advertisement Register (PHY_AN_ADV_x)
MODE[2:0] bits of the
(PHY_SPECIAL_MODES_x)
14.4.2.1). When configured low, auto-negotiation is
One pin configures the default for all 8
LED/GPIOs, but 8 separate bits are loaded by the
EEPROM Loader, allowing individual control over
each LED/GPIO.
If AMDIXCTL is set, this strap had no effect.
DATASHEET
Port x PHY Auto-Negotiation
LED Configuration Register
Auto-Negotiation (PHY_AN)
LED Configuration Register
Port x PHY Special Control/Status
Port x PHY Special Control/Status
Port x PHY Special Modes Register
41
is cleared.
is cleared.
enable bit
PIN / DEFAULT
VALUE
LED_EN
00b
AUTO_MDIX_1
0b
1b
Revision 1.7 (06-29-10)