LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 224
![no-image](/images/manufacturer_photos/0/6/632/standard_microsystems__smsc__sml.jpg)
LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NU.pdf
(458 pages)
Specifications of LAN9312-NU
Number Of Primary Switch Ports
2
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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- Download datasheet (5Mb)
Revision 1.7 (06-29-10)
BITS
13
12
11
10
9
8
7
6
Alternate MAC Address 1 Enable Port 0(Host MAC)
(MAC_ALT1_EN_MII)
This bit enables/disables the alternate MAC address 1 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 0
Alternate MAC Address 2 Enable Port 0(Host MAC)
(MAC_ALT2_EN_MII)
This bit enables/disables the alternate MAC address 2 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 0
Alternate MAC Address 3 Enable Port 0(Host MAC)
(MAC_ALT3_EN_MII)
This bit enables/disables the alternate MAC address 3 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 0
User Defined MAC Address Enable Port 0(Host MAC)
(MAC_USER_EN_MII)
This bit enables/disables the auxiliary MAC address on Port 0. The auxiliary
address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO
registers.
0: Disables auxiliary MAC address on Port 0
1: Enables auxiliary MAC address as a PTP address on Port 0
Lock Enable RX Port 0(Host MAC) (LOCK_RX_MII)
This bit enables/disables the RX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX
interrupt for Port 0 is ready set due to a previous capture.
0: Disables RX Port 0 Lock
1: Enables RX Port 0 Lock
Note:
Lock Enable TX Port 0(Host MAC) (LOCK_TX_MII)
This bit enables/disables the TX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX
interrupt for Port 0 is ready set due to a previous capture.
0: Disables TX Port 0 Lock
1: Enables TX Port 0 Lock
Note:
RESERVED
Lock Enable GPIO 9 (LOCK_GPIO_9)
This bit enables/disables the GPIO 9 lock. This lock prevents a 1588 capture
from overwriting the Clock value if the 1588_GPIO9 interrupt in the
Interrupt Status and Enable Register (1588_INT_STS_EN)
due to a previous capture.
0: Disables GPIO 9 Lock
1: Enables GPIO 9 Lock
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
224
is already set
1588
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
SMSC LAN9312
DEFAULT
Datasheet
0b
0b
0b
0b
1b
1b
1b
-
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