LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 257
![no-image](/images/manufacturer_photos/0/6/632/standard_microsystems__smsc__sml.jpg)
LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NU.pdf
(458 pages)
Specifications of LAN9312-NU
Number Of Primary Switch Ports
2
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.2.8.8
31:16
BITS
13:8
6:5
4:2
15
14
7
1
0
RESERVED
(See
RESERVED
Switch Looopback MII
When set, transmissions from the switch fabric Port 0(Host MAC) are not
sent to the Host MAC. Instead, they are looped back into the switch engine.
From the MAC viewpoint, this is effectively a FAR LOOPBACK.
If loopback is enabled during half-duplex operation, then the Enable Receive
Own Transmit bit in the
(MAC_RX_CFG_x)
ignore receive activity when transmitting in half-duplex mode.
This mode works even if the Isolate bit of the
Register (VPHY_BASIC_CTRL)
RESERVED
Switch Collision Test MII
When set, the collision signal to the switch fabric Port 0(Host MAC) is active
during transmission from the switch engine.
It is recommended that this bit be used only when using loopback mode.
RESERVED
Current Speed/Duplex Indication
This field indicates the current speed and duplex of the Virtual PHY link.
RESERVED
SQEOFF
This bit enables/disables the Signal Quality Error (Heartbeat) test.
0: SQE test enabled
1: SQE test disabled
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
This read/write register contains a current link speed/duplex indicator and SQE control.
[4]
Note
0
0
0
0
1
1
1
1
14.42)
Offset:
Index (decimal):
[3]
0
0
1
1
0
0
1
1
must be set for this port. Otherwise, the switch fabric will
Port x MAC Receive Configuration Register
[2]
1DCh
31
0
1
0
1
0
1
0
1
DESCRIPTION
is set.
DATASHEET
100Mbps
100Mbps
10Mbps
10Mbps
Speed
257
Virtual PHY Basic Control
Size:
RESERVED
RESERVED
RESERVED
RESERVED
half-duplex
half-duplex
full-duplex
full-duplex
Duplex
32 bits
Note 14.44
NASR
TYPE
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
Revision 1.7 (06-29-10)
Note 14.43
Note 14.45
DEFAULT
0b
0b
-
-
-
-
-
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