LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 302
![no-image](/images/manufacturer_photos/0/6/632/standard_microsystems__smsc__sml.jpg)
LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NU.pdf
(458 pages)
Specifications of LAN9312-NU
Number Of Primary Switch Ports
2
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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Revision 1.7 (06-29-10)
14.4.2.10
BITS
9:5
3:0
15
14
13
12
11
10
4
Auto-MDIX Control (AMDIXCTRL)
This bit is responsible for determining the source of Auto-MDIX control for
Port x. When set, the Manual MDIX and Auto MDIX straps
(manual_mdix_strap_1/auto_mdix_strap_1 for Port 1 PHY,
manual_mdix_strap_2/auto_mdix_strap_2 for Port 2 PHY) are overridden,
and Auto-MDIX functions are controlled using bit 14 (AMDIXEN) and bit 13
(AMDIXSTATE) of this register. When cleared, Auto-MDIX functionality is
controlled by the Manual MDIX and Auto MDIX straps by default. Refer to
Section 4.2.4, "Configuration Straps," on page 40
definitions.
0: Port x Auto-MDIX determined by strap inputs
1: Port x Auto-MDIX determined by bits 14 and 13
Auto-MDIX Enable (AMDIXEN)
When bit 15 (AMDIXCTRL) of this register is set, this bit is used in
conjunction with bit 13 (Auto-MDIX State) to control the Port x Auto-MDIX
functionality as shown in
Auto-MDIX State (AMDIXSTATE)
When bit 15 (AMDIXCTRL) of this register is set, this bit is used in
conjunction with bit 14 (Auto-MDIX Enable) to control the Port x Auto-MDIX
functionality as shown in
RESERVED
SQE Test Disable (SQEOFF)
This bit controls the disabling of the SQE test (Heartbeat). SQE test is
enabled by default.
0: SQE test enabled
1: SQE test disabled
Receive PLL Lock Control (VCOOFF_LP)
This bit controls the locking of the receive PLL. Setting this bit to 1 forces
the receive PLL 10M to lock on the reference clock at all times. When in this
mode, 10M data packets cannot be received.
0: Receive PLL 10M can lock on reference or line as needed (normal
operation)
1: Receive PLL 10M locked onto reference clock at all times
RESERVED
10Base-T Polarity State (XPOL)
This bit shows the polarity state of the 10Base-T.
0: Normal Polarity
1: Reversed Polarity
RESERVED
Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x)
This read/write register is used to control various options of the Port x PHY.
Note 14.61 Register bits designated as NASR are reset when the Port x PHY Reset is generated via
Index (decimal): 27
the
t h e
(PHY_BASIC_CONTROL_x)
Reset Control Register
R e s e t ( P H Y _ R S T )
Table
Table
DESCRIPTION
14.11.
14.11.
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
(RESET_CTL). The NASR designation is only applicable when
is set.
b i t o f t h e
302
for configuration strap
Size:
P o r t x P H Y B a s i c C o n t r o l R e g i s t e r
16 bits
Note 14.61
Note 14.61
Note 14.61
Note 14.61
Note 14.61
NASR
NASR
NASR
NASR
NASR
TYPE
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
SMSC LAN9312
DEFAULT
Datasheet
0b
0b
0b
0b
0b
0b
-
-
-
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