LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 182
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LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NU.pdf
(458 pages)
Specifications of LAN9312-NU
Number Of Primary Switch Ports
2
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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Revision 1.7 (06-29-10)
14.2.2.2
31:16
BITS
13:3
15
14
2
1
0
RESERVED
Force TX Status Discard (TXS_DUMP)
When a 1 is written to this bit, the TX Status FIFO is cleared of all pending
status DWORD’s and the TX status pointers are cleared to zero.
Force TX Data Discard (TXD_DUMP)
When a 1 is written to this bit, the TX Data FIFO is cleared of all pending
data and the TX data pointers are cleared to zero.
RESERVED
TX Status Allow Overrun (TXSAO)
When this bit is cleared, Host MAC data transmission is suspended if the
TX Status FIFO becomes full. Setting this bit high allows the transmitter to
continue operation with a full TX Status FIFO.
Note:
Transmitter Enable (TX_ON)
When this bit is set, the Host MAC transmitter is enabled. Any data in the
TX Data FIFO will be sent. This bit is cleared automatically when the
STOP_TX bit is set and the transmitter is halted.
Stop Transmitter (STOP_TX)
When this bit is set, the Host MAC transmitter will finish the current frame,
and will then stop transmitting. When the transmitter has stopped this bit will
clear. All writes to this bit are ignored while this bit is high.
Transmit Configuration Register (TX_CFG)
This register controls the Host MAC transmit functions.
This bit does not affect the operation of the
Interrupt
Offset:
(TSFF).
070h
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
182
Size:
TX Status FIFO Full
32 bits
TYPE
R/W
R/W
R/W
WO
WO
RO
RO
SC
SC
SC
SMSC LAN9312
DEFAULT
Datasheet
0b
0b
0b
0b
0b
-
-
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