MPC8315E-RDBA Freescale, MPC8315E-RDBA Datasheet - Page 70

• Manufacturer Part Number: MPC8315E-RDBA
• Manufacturer: Freescale

Specifications of MPC8315E-RDBA

• Lead Free Status / RoHS Status: Compliant

PCI Express
and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the
eye diagram.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
16.5.1
The AC timing and voltage parameters must be verified at the measurement point, as specified within
0.2 inches of the package pins, into a test/measurement load shown in
70
Compliance Test and Measurement Load
Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification
The reference impedance for return loss measurements is 50. to ground for
both the D+ and D- line (that is, as measured by a Vector Network Analyzer
with 50. probes—see
are optional for the return loss measurement.
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary.
MPC8315E PowerQUICC
(D+ D– Crossing Point)
V
RX-DIFF
= 0 mV
Figure
™
V
II Pro Processor Hardware Specifications, Rev. 0
RX-DIFFp-p-MIN
52). Note that the series capacitors, C
0.4 UI = T
NOTE
NOTE
RX-EYE-MIN
> 175 mV
(D+ D– Crossing Point)
V
RX-DIFF
Figure
= 0 mV
52.
PEACCTX
Freescale Semiconductor
,