MPC8315E-RDBA Freescale, MPC8315E-RDBA Datasheet - Page 67

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MPC8315E-RDBA

Manufacturer Part Number
MPC8315E-RDBA
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC8315E-RDBA

Lead Free Status / RoHS Status
Compliant
16.4.3
Table 55
specified at the component pins.
Freescale Semiconductor
Unit interval
Differential peak-to-peak
output voltage
Minimum receiver eye
width
Parameter
defines the specifications for the differential input at all receivers (RXs). The parameters are
Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications
Differential Receiver (RX) Input Specifications
MPC8315E PowerQUICC
Table 55. Differential Receiver (RX) Input Specifications
(D+ D– Crossing Point)
V
Symbol
RX-DIFFp-p
T
RX-EYE
V
TX-DIFF
UI
= 0 mV
566 mV (3 dB) >= V
0.7 UI = UI – 0.3 UI(J
Each UI is 400 ps ± 300 ppm.
UI does not account for
Spread Spectrum Clock
dictated variations.
V
V
The maximum interconnect
media and Transmitter jitter
that can be tolerated by the
Receiver can be derived as
T
U
II Pro Processor Hardware Specifications, Rev. 0
RX-MAX-JITTER
RX-DIFFp-p
RX-D-
RX-EYE
V
V
[De-emphasized Bit]
TX-DIFFp-p-MIN
TX-DIFFp-p-MIN
|
[Transition Bit]
[Transition Bit]
= 0.6 UI.
Comments
TX-DIFFp-p-MIN
= 2*|V
= 800 mV
= 800 mV
= 1 -
TX-TOTAL-MAX
RX-D+
>= 505 mV (4 dB)
-
(D+ D– Crossing Point)
)
V
TX-DIFF
399.88
0.175
Min
0.4
= 0 mV
Typical
400
400.12
1.200
Max
Units
ps
UI
V
PCI Express
Notes
2, 3
1
2
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