MPC8315E-RDBA Freescale, MPC8315E-RDBA Datasheet - Page 100

• Manufacturer Part Number: MPC8315E-RDBA
• Manufacturer: Freescale

Specifications of MPC8315E-RDBA

• Lead Free Status / RoHS Status: Compliant

Clocking
24.2
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
not listed in
24.3
To simplify the PLL configurations, the MPC8315E might be separated into two clock domains. The first
domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The clock domains are independent, and each of their PLLs are
configured separately. Both of the domains has one common input clock.
configurations for 33, 25, and 66 MHz input clocks.
100
Conf. No.
1
1
2
Core VCO frequency = core frequency × VCO divider.
0–1
nn
11
00
01
00
01
00
01
00
01
00
01
Suggested PLL Configurations
Core PLL Configuration
RCWL[COREPLL]
Table 76
SPMF
0100
0100
Core VCO frequency = core frequency × VCO divider
range of 400–800 MHz.
VCO divider has to be set properly so that the core VCO frequency is in the
nnnn
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
2–5
MPC8315E PowerQUICC
should be considered as reserved.
Table 76
Core\PLL
0000100
0000101
6
0
n
0
0
1
1
0
0
1
1
0
0
shows the encodings for RCWL[COREPLL]. COREPLL values that are
Table 77. Suggested PLL Configurations
Table 76. e300 Core PLL Configuration
(PLL off, csb_clk clocks core directly)
Input Clock Frequency (MHz) CSB Frequency (MHz) Core Frequency (MHz)
core_clk : csb_clk Ratio
™
II Pro Processor Hardware Specifications, Rev. 0
PLL bypassed
33.33
25
1.5:1
1.5:1
2.5:1
2.5:1
N/A
1:1
1:1
2:1
2:1
3:1
3:1
NOTE
(PLL off, csb_clk clocks core directly)
133.33
100
Table 77
VCO Divider
PLL bypassed
N/A
2
4
2
4
2
4
2
4
2
4
shows suggested PLL
Freescale Semiconductor
1
266.66
250