CS1D-BC042D Omron, CS1D-BC042D Datasheet - Page 352

• Manufacturer Part Number: CS1D-BC042D
• Description: CS1D Dual CPU Exp
• Manufacturer: Omron

Specifications of CS1D-BC042D

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Sharing Index Registers
8-18 Data Registers
Examples
Range of Values
Data Register Initialization
Data Registers
1,2,3...
This setting can be made from the CX-Programmer.
To share Index Registers among tasks, remove the check from (deselect) the
Use IRs/DRs independently per task Option.
The sixteen Data Registers (DR0 to DR15) are used to offset the PLC mem-
ory addresses in Index Registers when addressing words indirectly.
The value in a Data Register can be added to the PLC memory address in an
Index Register to specify the absolute memory address of a bit or word in I/O
memory. Data Registers contain signed binary data, so the content of an
Index Register can be offset to a lower or higher address.
Bits in Data Registers cannot be force-set or force-reset.
Regular instructions can be used to store data in Data Registers.
The following examples show how Data Registers are used to offset the PLC
memory addresses in Index Registers.
The contents of data registers are treated as signed binary data and thus
have a range of –32,768 to 32,767.
The Data Registers will be cleared in the following cases:
1. The operating mode is changed from PROGRAM mode to RUN/MONITOR
8000 to FFFF
0000 to 7FFF
Hexadecimal content
LD
MOV(021) #0001 DR0 ,IR1
mode or vice-versa and the IOM Hold Bit is OFF.
Set to a base value
with MOVR(560) or
MOVRW(561).
Set with a regular
instruction.
DR0 ,IR0
–32,768 to –1
0 to 32,767
Decimal equivalent
Pointer
Adds the contents of DR0 to the contents
of IR0 and loads the bit at that PLC mem-
ory address.
Adds the contents of DR0 to the contents
of IR1 and writes #0001 to that PLC
memory address.
I/O Memory
Section 8-18
317