CS1D-BC042D Omron, CS1D-BC042D Datasheet - Page 294

• Manufacturer Part Number: CS1D-BC042D
• Description: CS1D Dual CPU Exp
• Manufacturer: Omron

Specifications of CS1D-BC042D

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I/O Memory Areas
Counter Completion Flags
Counter PVs
Condition Flags
Clock Pulses
Task Flag Area (TK)
Index Registers (IR)
Data Registers (DR)
8-2-3
Content After Fatal Errors, Forced Set/Reset Usage
CIO
Area
I/O Area
Data Link Area
CPU Bus Units
Special I/O Unit Area
Inner Board Area
CS-series DeviceNet
Area
Internal I/O Area
Data Area Properties
Area
Basic I/O Units
Controller Link data
links
CPU Bus Units
Special I/O Units
Inner Boards
DeviceNet Slaves or
Master
None
External allocation
These flags are read as bits. A Completion Flag is turned ON by the system
when the corresponding counter counts out (the set value is reached).
The PVs are read and written as words (16 bits). The PVs count up or down
as the counter operates.
These flags include the Arithmetic Flags such as the Error Flag and Equals
Flag which indicate the results of instruction execution as well as the Always
ON and Always OFF Flags. The Condition Flags are specified with labels
(symbols) rather than addresses.
The Clock Pulses are turned ON and OFF by the CPU Unit’s internal timer.
These bits are specified with labels (symbols) rather than addresses.
Task Flags range from TK00 to TK31 and correspond to cyclic tasks 0 to 31. A
Task Flag will be ON when the corresponding cyclic task is in executable
(RUN) status and OFF when the cyclic task hasn’t been executed (INI) or is in
standby (WAIT) status.
These registers (IR0 to IR15) are used to store PLC memory addresses
(absolute memory addresses in RAM) to indirectly address words in I/O mem-
ory. The Index Registers can be used separately in each task or they can be
shared by all tasks.
These registers (DR0 to DR15) are used together with the Index Registers.
When a Data Register is input just before an Index Register, the content of the
Data Register is added to the PLC memory address in the Index Register to
offset that address. The Data Registers are used separately in each task or
they can be shared by all tasks.
Retained
Execution of FALS(007)
IOM Hold
Bit OFF
Fatal Error Generated
Retained
IOM Hold
Bit ON
IOM Hold
Cleared
Bit OFF
Other Fatal Error
Retained
IOM Hold
Bit ON
Section 8-2
Yes
Forced Reset
Forced Set/
Functions
Usable?
259