CS1D-BC042D Omron, CS1D-BC042D Datasheet - Page 159

• Manufacturer Part Number: CS1D-BC042D
• Description: CS1D Dual CPU Exp
• Manufacturer: Omron

Specifications of CS1D-BC042D

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Duplex CPU Units
Operational
Restrictions
Instruction
Restrictions
124
Note If the mode is changed from Duplex Mode to Simplex Mode during execution
of a timer instruction, the accuracy in the first cycle following the mode switch
is less than normal (as shown below).
TIM, TIMX, TIMH(015), TIMHX(551), TTIM(087), TTIMX(555), TIML(542),
TIMLX(553), MTIM(543), MTIMX(554), TIMW(813), TIMWX(816),
TMHW(815), TMHWX(817) : (10 ms + cycle time) 10 ms
TMHH(540), TMHHX(552) : (10 ms + cycle time) 20 ms
Reference: Timer accuracy for the CS1-H is as follows:
TIM, TIMX, TIMH(015), TIMHX(551), TTIM(087), TTIMX(555), TIML(542),
TIMLX(553), MTIM(543), MTIMX(554), TIMW(813), TIMWX(816),
TMHW(815), TMHWX(817) : 0 to 10 ms
TMHH(540), TMHHX(552) : 0 to 1 ms
• Duplex operation is possible for EM file memory.
• Interrupts (including scheduled interrupt tasks, external interrupt tasks,
• Parallel processing for peripheral servicing (Parallel Processing Mode and
• The clock function is synchronized with the active CPU Unit.
• Instructions with the immediate refresh option (!) cannot be used. (The
• The accuracy of timer instructions (TIM, TIMX, TIMH(015), TIMHX(551),
• PV refresh operations during timer instruction jumps, or while a block pro-
• Background execution cannot be used for text string processing instruc-
• Interrupt control instructions (MSKS, MSKR, CLI) and peripheral servicing
• Execution of the following instructions (called “synchronized instructions”)
and power OFF interrupt tasks) cannot be used.
Peripheral Servicing Priority Mode) cannot be executed.
IORF instruction, however, is available.)
TMHH(540), TMHHX(552), TTIM(087), TTIMX(555), TIMW(813),
TIMWX(816), TMHW(815), TMHWX(817), TIML(542), TIMLX(553),
MTIM(543), and MTIMX(554)) is less than for CS1-H CPU Units. The
accuracy is as follows:
TIM, TIMX, TIMH(015), TIMHX(551), TMHH(540), TMHHX(552),
TTIM(087), TTIMX(555), TIML(542), TIMLX(553), MTIM(543),
MTIMX(554), TIMW(813), TIMWX(816), TMHW(815), TMHWX(817):
gram is stopped, are described below. (Operation is different from CS1-H
CPU Units.)
a) TIM, TIMX, TIMH(015), TIMHX(551), TMHH(540), TMHHX(552),
b) TIMW(813), TIMWX(816), TMHW(815), and TMHWX(817):
tions, table data instructions, or data shift instructions.
disable/enable instructions (IOSP/IORS) cannot be used. (They will be
executed as NOPs.)
is synchronized between the two CPU Units, so their instruction execution
(10 ms + cycle time)
TTIM(087), TTIMX(555):
When a jump is executed for a JMP, CJMP, or CMPN-JME instructions,
the timer PV is not refreshed (unlike CS1-H CPU Units). The next time
the instruction is executed (i.e., the next time the jump is not made) the
timer is refreshed for the period of time that elapsed since it was last
refreshed.
The timer PV is not refreshed when the BPRG instruction input condi-
tion is OFF or when the block program is paused by the BPPS instruc-
tion. (It is refreshed for CS1-H CPU Units.)
Section 3-1