ADE7569ASTZF16-RL Analog Devices Inc, ADE7569ASTZF16-RL Datasheet - Page 40

• Manufacturer Part Number: ADE7569ASTZF16-RL
• Description: IC,Power Metering,QFP,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7569ASTZF16-RL

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7566/ADE7569
Table 37. Interrupt Status Register 2 SFR (MIRQSTM, 0xDD)
Bit No.
7
6
5
4
3
2
1
0
1
Table 38. Interrupt Status Register 3 SFR (MIRQSTH, 0xDE)
Bit No.
7
6
5
4
3
2
1
0
Table 39. Interrupt Enable Register 1 SFR (MIRQENL, 0xD9)
Bit No.
7 to 5
4
3
2
1
0
1
Table 40. Interrupt Enable Register 2 SFR (MIRQENM, 0xDA)
Bit No.
7
6
5
4
3
2
1
0
1
This function is not available in the ADE7566 part.
This function is not available in the ADE7566 part.
This function is not available in the ADE7566 part.
Interrupt Flag
CF2
CF1
VAEOF
REOF
AEOF
VAEHF
REHF
AEHF
Interrupt Flag
RESET
–
WFSM
PKI
PKV
CYCEND
ZXTO
ZX
Interrupt Enable Bit
CF2
CF1
VAEOF
REOF
AEOF
VAEHF
REHF
AEHF
Interrupt Enable Bit
VARSIGN
APSIGN
VANOLOAD
RNOLOAD
APNOLOAD
Reserved
1
1
1
1
1
1
Description
Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if CF2 pulse output is not enabled by
clearing Bit 2 of MODE1 register.
Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if CF1 pulse output is not enabled by
clearing Bit 1 of MODE1 register.
Logic 1 indicates that the VAHR register has overflowed.
Logic 1 indicates that the VARHR register has overflowed.
Logic 1 indicates that the WATTHR register has overflowed.
Logic 1 indicates that the VAHR register is half-full.
Logic 1 indicates that the VARHR register is half-full.
Logic 1 indicates that the WATTHR register is half-full.
Description
Indicates the end of a reset (for both software and hardware reset).
Reserved.
Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7).
Logic 1 indicates that current channel has exceeded the IPKLVL value
Logic 1 indicates that voltage channel has exceeded the VPKLVL value.
Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles.
Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles.
Logic 1 indicates detection of a zero crossing in the voltage channel.
Description
When this bit is set, a CF2 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set, a CF1 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
Description
Reserved.
When set, the VARSIGN bit set creates a pending ADE interrupt to the 8052 core.
When set, the APSIGN bit set creates a pending ADE interrupt to the 8052 core.
When set, the VANOLOAD bit set creates a pending ADE interrupt to the 8052 core.
When set, the RNOLOAD bit set creates a pending ADE interrupt to the 8052 core.
When set, the APNOLOAD bit set creates a pending ADE interrupt to the 8052 core.
Rev. PrA | Page 40 of 136
Preliminary Technical Data