ADE7569ASTZF16-RL Analog Devices Inc, ADE7569ASTZF16-RL Datasheet - Page 108

• Manufacturer Part Number: ADE7569ASTZF16-RL
• Description: IC,Power Metering,QFP,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7569ASTZF16-RL

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7566/ADE7569
Table 116. RTC Configuration SFR (TIMECON, 0xA1)
Bit No.
7
6
5 to 4
3
2
1
0
Table 117. Hundredths of a Second Counter SFR (HTHSEC, 0xA2)
Bit No.
7 to 0
Table 118. Seconds Counter SFR (SEC, 0xA3)
Bit No.
7 to 0
Table 119. Minutes Counter SFR (MIN, 0xA4)
Bit No.
7 to 0
Table 120. Hours Counter SFR (HOUR, 0xA5)
Bit No.
7 to 0
Mnemonic
MIDNIGHT
TFH
ITS[1:0]
SIT
ALARM
ITEN
RTCEN
Mnemonic
HTHSEC
Mnemonic
SEC
Mnemonic
MIN
Mnemonic
HOUR
Default
0
0
0
0
0
0
1
Default
0
Default
0
Default
0
Default
0
Description
Midnight Flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to
indicate that the midnight event has been serviced. In twenty-four hour mode, the midnight flag is
raised once a day at midnight.
Twenty-Four Hour Mode. This bit is retained during a watchdog reset or an external reset. It is reset after
a power on reset (POR).
TFH
0
1
Interval Timer Time-Base Selection.
ITS[1:0]
00
01
10
11
Interval Timer 1 Time Alarm.
SIT
0
1
Interval Timer Alarm Flag. This bit is set when the configured time interval has elapsed. It can be cleared
by the user to indicate that the alarm event has been serviced. This bit cannot be set to 1 by user code.
Interval Timer Enable.
ITEN
0
1
RTC Enable. Also Temperature, Battery and Supply ADC Background Strobe Enable. Note that the RTC is
always enabled.
Description
This counter updates every 1/128 sec, referenced from the calibrated 32 kHz clock. It overflows from
127 to 00, incrementing the seconds counter (SEC). This register is retained during a watchdog reset or
an external reset. It is reset after a POR.
Description
This counter updates every second, referenced from the calibrated 32 kHz clock. It overflows from 59 to 00,
incrementing the minutes counter (MIN). This register is retained during a watchdog reset or an external
reset. It is reset after a POR.
Description
This counter updates every minute, referenced from the calibrated 32 kHz clock. It overflows from 59 to 00,
incrementing the hours counter, HOUR. This register is retained during a watchdog reset or an external
reset. It is reset after a POR.
Description
This counter updates every hour, referenced from the calibrated 32 kHz clock. If the TFH bit in the RTC
Configuration SFR (TIMECON, 0xA1) is set, the HOUR SFR overflows from 23 to 00, setting the MIDNIGHT
bit and creating a pending RTC interrupt. If the TFH bit is cleared, the HOUR SFR overflows from 255 to 00,
setting the MIDNIGHT bit and creating a pending RTC interrupt. This register is retained during a
watchdog reset or an external reset. It is reset after a POR.
Result
256-Hour Mode. The HOUR register rolls over from 255 to 0.
24-Hour Mode. The HOUR register rolls over from 23 to 0.
Result (Time base)
1/128 sec.
Second.
Minute.
Hour.
Result
The ALARM flag is set after INTVAL counts and then another interval count starts.
The ALARM flag is set after one time interval.
Result
The interval timer is disabled. The 8-bit interval timer counter is reset.
Set this bit to enable the interval timer. The RTCEN bit must also be set to enable the
interval timer.
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Preliminary Technical Data