ADE7518ASTZF16-RL Analog Devices Inc, ADE7518ASTZF16-RL Datasheet - Page 50
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ADE7518ASTZF16-RL
Manufacturer Part Number
ADE7518ASTZF16-RL
Description
1-Phase Energy Meter IC
Manufacturer
Analog Devices Inc
Datasheet
1.ADE7518ASTZF16.pdf
(128 pages)
Specifications of ADE7518ASTZF16-RL
Applications
Energy Measurement
Core Processor
8052
Program Memory Type
FLASH (16 kB)
Controller Series
ADE75xx
Ram Size
512 x 8
Interface
I²C, SPI, UART
Number Of I /o
20
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADE7518ASTZF16-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADE7518
ACTIVE ENERGY CALCULATION
As stated in the Active Power Calculation section, power is
defined as the rate of energy flow. This relationship can be
expressed mathematically in Equation 11.
where:
P is power.
E is energy.
Conversely, energy is given as the integral of power.
The ADE7518 achieves the integration of the active power signal by
continuously accumulating the active power signal in an internal,
nonreadable, 49-bit energy register. The active energy register
(WATTHR[23:0]) represents the upper 24 bits of this internal
register. This discrete time accumulation or summation is
equivalent to integration in continuous time. Equation 13
expresses the relationship.
where:
n is the discrete time sample number.
T is the sample period.
The discrete time sample period (T) for the accumulation
register in the ADE7518 is 1.22 μs (5/MCLK). In addition to
calculating the energy, this integration removes any sinusoidal
components that may be in the active power signal. Figure 52
P =
E
E
=
=
∫
dE
∫
dt
P
p
) (
t
) (
t
CURRENT
CHANNEL
CHANNEL
VOLTAGE
dt
dt
=
lim
t
→
0
⎧
⎨
⎩
∑
n
∞
=
T
1
p
(
nT
ACTIVE POWER
)
LPF2
MCLK
sgn
×
SIGNAL
5
TIME (nT)
T
WATTOS[15:0]
⎫
⎬
⎭
2
6
2
+
5
+
WAVEFORM
2
REGISTER
–6
VALUES
2
–7
Figure 52. Active Energy Calculation
2
–8
FOR WAVEFORM
SAMPLING
WGAIN[11:0]
Rev. 0 | Page 50 of 128
(11)
(12)
(13)
WDIV[7:0]
%
shows this discrete time integration or accumulation. The active
power signal in the waveform register is continuously added to
the internal active energy register.
The active energy accumulation depends on the setting of the
POAM and ABSAM bits in the ACCMODE register (0x0F).
When both bits are cleared, the addition is signed and, therefore,
negative energy is subtracted from the active energy contents.
When both bits are set, the ADE7518 is set to be in the more
restrictive mode, the positive-only accumulation mode.
When POAM in the ACCMODE register (0x0F) is set, only posi-
tive power contributes to the active energy accumulation. When
ABSAM in the ACCMODE register (0x0F) is set, the absolute
active power is used for the active energy accumulation (see the
Watt-Absolute Accumulation Mode section).
The output of the multiplier is divided by the value in the
WDIV register. If the value in the WDIV register is equal to 0,
the internal active energy register is divided by 1. WDIV is an
8-bit unsigned register. After dividing by WDIV, the active
energy is accumulated in a 49-bit internal energy accumulation
register. The upper 24 bits of this register are accessible through
a read to the active energy register (WATTHR[23:0]). A read to
the RWATTHR register returns the content of the WATTHR
register, and the upper 24 bits of the internal register are cleared.
As shown in Figure 52, the active power signal is accumulated
in an internal 49-bit signed register. The active power signal can
be read from the waveform register by setting the WAVMODE
register (0x0D) and setting the WFSM bit in the Interrupt Enable 3
SFR (MIRQENH, 0xDB). Like the current and voltage channels
waveform sampling modes, the waveform data is available at a
sample rate of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS.
TO
DIGITAL-TO-FREQUENCY
CONVERTER
+
+
48
23
WATTHR[23:0]
OUTPUTS FROM THE LPF2 ARE
ACCUMULATED (INTEGRATED) IN
THE INTERNAL ACTIVE ENERGY REGISTER
0
UPPER 24 BITS ARE
ACCESSIBLE THROUGH
WATTHR[23:0] REGISTER
0