ADE7518ASTZF16-RL Analog Devices Inc, ADE7518ASTZF16-RL Datasheet - Page 27

• Manufacturer Part Number: ADE7518ASTZF16-RL
• Description: 1-Phase Energy Meter IC
• Manufacturer: Analog Devices Inc

Specifications of ADE7518ASTZF16-RL

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE7518 can be configured to generate a PSM interrupt
when the source of V
battery switchover. Setting the EBSO bit in the Power Management
Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate
a PSM interrupt (see Table 19).
The ADE7518 can also be configured to generate an interrupt
when the source of V
that the V
in the Power Management Interrupt Enable SFR (IPSME, 0xEC)
enables this event to generate a PSM interrupt.
The flags in the IPSMF SFR for these interrupts, FBSO and
FPSR, are set regardless of whether the respective enable bits
have been set. The battery switchover and power supply restore
event flags, FBSO and FPSR, are latched. These events must be
cleared by writing 0 to these bits. Bit 6 in the Peripheral
Configuration SFR (PERIPH, 0xF4), VSWSOURCE, tracks the
source of V
and cleared when V
DD
SWOUT
power supply has been restored. Setting the EPSR bit
. The bit is set when V
SWOUT
SWOUT
SWOUT
is connected to V
changes from V
changes from V
SWOUT
DD
BAT
BAT
is connected to V
to V
.
to V
BAT
DD
, indicating
, indicating
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DD
V
The V
bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8)
is set when the V
EVDCIN bit in the IPSME SFR enables this event to generate
a PSM interrupt. This event, which is associated with the SAG
monitoring, can be used to detect a power supply (V
compromised and to trigger further actions prior to deciding a
switch of V
SAG Monitor PSM Interrupt
The ADE7518 energy measurement DSP monitors the ac voltage
input at the V
to set the threshold for a line voltage SAG event. The FSAG bit
in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is
set if the line voltage stays below the level set in the SAGLVL
register for the number of line cycles set in the SAGCYC register.
See the Line Voltage SAG Detection section for more informa-
tion. Setting the ESAG bit in the Power Management Interrupt
Enable SFR (IPSME, 0xEC) enables this event to generate a
PSM interrupt.
DCIN
Monitor PSM Interrupt
DCIN
voltage is monitored by a comparator. The FVDCIN
DD
to V
P
and V
DCIN
BAT
.
input level is lower than 1.2 V. Setting the
N
input pins. The SAGLVL register is used
ADE7518
DD
) being