MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 52

MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM

MEDIA5200KIT1

Manufacturer Part Number
MEDIA5200KIT1
Description
MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MEDIA5200KIT1

Processor To Be Evaluated
MPC5200B
Data Bus Width
32 bit
Interface Type
Ethernet, USB
Lead Free Status / Rohs Status
Not Compliant
52
(CLKPOL=0)
(CLKPOL=1)
Sym
10
1
2
3
4
5
6
7
8
9
Output
MOSI
MISO
Input
Input
Input
SCK
Input
Sequential Transfer delay, programable in the PSC CTUR / CTLR
SCK
Slave select clock delay, programable in the PSC CCS register
SS
Table 48. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)
SCK cycle time, programable in the PSC CCS register
Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)
SCK pulse width, 50% SCK duty cycle
6
3
4
Slave disable lag time
Input Data setup time
Output timing is specified at a nominal 50 pF load.
Input Data hold time
Output data valid
Clock falling time
Clock rising time
Description
2
register
MPC5200B Data Sheet, Rev. 4
1
7
2
NOTE
5
30.0
15.0
30.0
15.0
Min
6.0
1.0
8
Max
8.9
8.9
7.9
7.9
Freescale Semiconductor
9
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SpecID
A15.46
A15.47
A15.48
A15.49
A15.50
A15.51
A15.52
A15.53
A15.54
A15.55

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