MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 45
MEDIA5200KIT1
Manufacturer Part Number
MEDIA5200KIT1
Description
MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
Manufacturer
Freescale Semiconductor
Specifications of MEDIA5200KIT1
Processor To Be Evaluated
MPC5200B
Data Bus Width
32 bit
Interface Type
Ethernet, USB
Lead Free Status / Rohs Status
Not Compliant
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1.3.13
The CAN functions are available as RX and TX pins at normal IO pads (I
WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.
1.3.14
Freescale Semiconductor
1
(CLKPOL=0)
(CLKPOL=1)
Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
Sym
1
2
4
6
7
8
9
Output
MSCAN
I
MOSI
2
MISO
Input
Input
Input
SCK
Input
SCK
C
Start condition setup time (for repeated start condition
SS
Figure 35. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
Table 40. I
Stop condition setup time
Start condition hold time
4
3
Data setup time
Clock high time
Clock low time
Data hold time
Description
2
only)
2
C Input Timing Specifications—SCL and SDA
5
MPC5200B Data Sheet, Rev. 4
1
2
6
2
C1+GPTimer or PSC2). There is no filter for the
Min
0.0
0.0
2
4
8
2
2
Max
—
—
—
—
—
—
—
7
IP-Bus Cycle
IP-Bus Cycle
IP-Bus Cycle
IP-Bus Cycle
IP-Bus Cycle
Units
8
ns
ns
(1)
(1)
(1)
(1)
(1)
SpecID
A13.1
A13.2
A13.3
A13.4
A13.5
A13.6
A13.7
45
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