MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 43

MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM

MEDIA5200KIT1

Manufacturer Part Number
MEDIA5200KIT1
Description
MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MEDIA5200KIT1

Processor To Be Evaluated
MPC5200B
Data Bus Width
32 bit
Interface Type
Ethernet, USB
Lead Free Status / Rohs Status
Not Compliant
Freescale Semiconductor
1
(CLKPOL=0)
(CLKPOL=1)
Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
Sym
10
1
2
3
4
5
6
7
8
9
Output
MOSI
MISO
Input
Input
Input
SCK
Input
SCK
SS
Table 38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)
Figure 33. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)
Slave select to clock delay
4
Sequential Transfer delay
3
Clock high or low time
Slave disable lag time
Input Data setup time
Input Data hold time
6
Output data valid
Clock falling time
Clock rising time
Output timing is specified at a nominal 50 pF load.
Description
Cycle time
2
MPC5200B Data Sheet, Rev. 4
1
5
2
NOTE
7
15.0
20.0
20.0
15.0
Min
4
2
1
1024
Max
20.0
512
7.9
7.9
8
IP-Bus Cycle
IP-Bus Cycle
IP-Bus Cycle
Units
9
ns
ns
ns
ns
ns
ns
ns
(1)
(1)
(1)
SpecID
A11.21
A11.22
A11.23
A11.24
A11.25
A11.26
A11.27
A11.28
A11.29
A11.30
43

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