MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 19

• Manufacturer Part Number: MEDIA5200KIT1
• Description: MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
• Manufacturer: Freescale Semiconductor

Specifications of MEDIA5200KIT1

• Processor To Be Evaluated: MPC5200B
• Data Bus Width: 32 bit
• Interface Type: Ethernet, USB
• Lead Free Status / Rohs Status: Not Compliant

1.3.6.3
The SDRAM Memory Controller uses a 1/4 period delayed MDQS strobe to capture the MDQ data. The 1/4 period delay value
is calculated automatically by hardware.
Freescale Semiconductor
data
t
data
mem_clk
MBA (Bank Selects)
Sym
t
t
valid
hold
DQM (Data Mask)
setup
hold
Control Signals
MA (Address)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
MDQ (Data)
MEM_CLK
Memory Interface Timing-DDR SDRAM Read Command
valid after rising edge of MEM_CLK
hold after rising edge of MEM_CLK
Control Signals, Address and MBA
Control Signals, Address and MBA
Setup time relative to MDQS
Hold time relative to MDQS
Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing
MEM_CLK period
Description
t
t
t
valid
valid
valid
Table 20. DDR SDRAM Memory Read Timing
Active
Row
t
t
t
data
hold
hold
hold
DM
valid
MPC5200B Data Sheet, Rev. 4
valid
NOP
WRITE
Column
t
mem_clk
Min
7.5
2.6
—
—
DM
data
× 0.5
NOP
hold
hold
NOP
t
mem_clk
NOP
Max
0.4
× 0.5 + 0.4
—
—
—
NOP
Units
ns
ns
ns
ns
ns
NOP
SpecID
A5.16
A5.17
A5.18
A5.19
A5.15
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