MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 51

MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM

MEDIA5200KIT1

Manufacturer Part Number
MEDIA5200KIT1
Description
MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MEDIA5200KIT1

Processor To Be Evaluated
MPC5200B
Data Bus Width
32 bit
Interface Type
Ethernet, USB
Lead Free Status / Rohs Status
Not Compliant
Freescale Semiconductor
(CLKPOL=0)
(CLKPOL=1)
Sym
1
2
3
4
5
6
7
8
9
Output
Output
Output
Output
MOSI
MISO
SCK
Input
Minimum Sequential Transfer delay = 2 × IP Bus clock cycle time
SCK
SS
Table 47. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)
SCK cycle time, programable in the PSC CCS register
Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)
4
SCK pulse width, 50% SCK duty cycle
6
3
Output data valid after SCK
Output data valid after SS
Slave select clock delay
Slave disable lag time
Input Data setup time
Output timing is specified at a nominal 50 pF load.
Input Data hold time
Description
2
5
7
MPC5200B Data Sheet, Rev. 4
1
6
2
NOTE
10
11
7
10
11
30.0
30.0
15.0
Min
1.0
1.0
1.0
0.0
8
14.0
Max
14.0
9
Units
ns
ns
ns
ns
ns
ns
ns
ns
SpecID
A15.37
A15.38
A15.39
A15.40
A15.41
A15.42
A15.43
A15.44
A15.45
51

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