MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 50

MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM

MEDIA5200KIT1

Manufacturer Part Number
MEDIA5200KIT1
Description
MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MEDIA5200KIT1

Processor To Be Evaluated
MPC5200B
Data Bus Width
32 bit
Interface Type
Ethernet, USB
Lead Free Status / Rohs Status
Not Compliant
1.3.16.4
50
Sym
10
11
1
2
3
4
5
6
7
8
9
(SIR / FIR / MIR)
SPI Mode
Sequential Transfer delay, programable in the PSC CTUR / CTLR
Slave select clock delay, programable in the PSC CCS register
IrDA_TX
Table 46. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)
SCK cycle time, programable in the PSC CCS register
Output Data valid after Slave Select (SS)
SCK pulse width, 50% SCK duty cycle
Figure 40. Timing Diagram — IrDA Transmit Line
Output Data valid after SCK
Slave disable lag time
Input Data setup time
Output timing is specified at a nominal 50 pF load.
Input Data hold time
Clock falling time
Clock rising time
1
Description
register
MPC5200B Data Sheet, Rev. 4
2
NOTE
4
3
30.0
15.0
30.0
15.0
Min
6.0
1.0
Max
8.9
8.9
8.9
7.9
7.9
Freescale Semiconductor
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SpecID
A15.26
A15.27
A15.28
A15.29
A15.30
A15.31
A15.32
A15.33
A15.34
A15.35
A15.36

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