MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 42

MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM

MEDIA5200KIT1

Manufacturer Part Number
MEDIA5200KIT1
Description
MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MEDIA5200KIT1

Processor To Be Evaluated
MPC5200B
Data Bus Width
32 bit
Interface Type
Ethernet, USB
Lead Free Status / Rohs Status
Not Compliant
42
1
(CLKPOL=0)
(CLKPOL=1)
Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
Sym
1
2
3
4
5
6
7
8
9
Output
Output
Output
Output
MOSI
MISO
SCK
Input
SCK
SS
Table 37. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)
Output Data valid after Slave Select (SS)
Figure 32. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)
4
Output Data valid after SCK
Slave select to clock delay
Sequential Transfer delay
Clock high or low time
Slave disable lag time
6
Input Data setup time
Input Data hold time
3
Description
Cycle time
Output timing is specified at a nominal 50 pF load.
2
5
7
MPC5200B Data Sheet, Rev. 4
1
6
2
NOTE
10
11
7
50.0
15.0
15.0
Min
0.0
4
2
1
10
11
1024
Max
50.0
50.0
512
8
IP-Bus Cycle
IP-Bus Cycle
IP-Bus Cycle
Units
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
9
(1)
(1)
(1)
SpecID
A11.12
A11.13
A11.14
A11.15
A11.16
A11.17
A11.18
A11.19
A11.20

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