P0071 Terasic Technologies Inc, P0071 Datasheet - Page 55
![no-image](/images/manufacturer_photos/0/6/659/terasic_technologies_inc_sml.jpg)
P0071
Manufacturer Part Number
P0071
Description
TPAD MULTIMEDIADEVELOPMENT KIT
Manufacturer
Terasic Technologies Inc
Series
tPAD, Cyclone®IVr
Specifications of P0071
Main Purpose
Reference Design, Tablet
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
EP4CE115
Primary Attributes
8-Inch TFT LCD, LED Backlight
Secondary Attributes
5-Megapixel Digital Image Sensor
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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to I2C_SDA. Because audio chip, TV decoder chip and HSMC share one I2C bus, therefore
audio and video chip won’t function correctly.
4
The DE2-115 board uses the ZT3232 transceiver chip and a 9-pin DB9 connector for RS-232
communications. For detailed information on how to use the transceiver, please refer to the
datasheet, which is available on the manufacturer‟s website, or in the DE2_115_datasheets\RS-232
folder on the DE2-115 System CD.
the Cyclone IV E FPGA pin assignments.
Signal Name
AUD_ADCLRCK
AUD_ADCDAT
AUD_DACLRCK
AUD_DACDAT
AUD_XCK
AUD_BCLK
I2C_SCLK
I2C_SDAT
4
.
.
1
1
2
2
Note: If the HSMC loopback adapter is mounted, the I2C_SCL will be directly routed back
R
R
S
S
-
-
2
2
3
3
2
2
Figure 4-23 Connections between FPGA and Audio CODEC
S
S
FPGA Pin No.
PIN_C2
PIN_D2
PIN_E3
PIN_D1
PIN_E1
PIN_F2
PIN_B7
PIN_A8
e
e
r
Table 4-17 Audio CODEC Pin Assignments
r
i
i
a
a
l
l
P
P
o
o
Figure 4-24
r
r
t
t
Description
Audio CODEC ADC LR Clock
Audio CODEC ADC Data
Audio CODEC DAC LR Clock
Audio CODEC DAC Data
Audio CODEC Chip Clock
Audio CODEC Bit-Stream Clock
I2C Clock
I2C Data
54
shows the related schematics, and
Table 4-18
I/O Standard
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
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