P0071 Terasic Technologies Inc, P0071 Datasheet - Page 41
![no-image](/images/manufacturer_photos/0/6/659/terasic_technologies_inc_sml.jpg)
P0071
Manufacturer Part Number
P0071
Description
TPAD MULTIMEDIADEVELOPMENT KIT
Manufacturer
Terasic Technologies Inc
Series
tPAD, Cyclone®IVr
Specifications of P0071
Main Purpose
Reference Design, Tablet
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
EP4CE115
Primary Attributes
8-Inch TFT LCD, LED Backlight
Secondary Attributes
5-Megapixel Digital Image Sensor
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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LCD_DATA[2]
LCD_DATA[1]
LCD_DATA[0]
LCD_EN
LCD_RW
LCD_RS
LCD_ON
LCD_BLON
4
The DE2-115 development board contains a HSMC interface to provide a mechanism for extending
the peripheral-set of a FPGA host board by means of add-on cards. This can address today‟s high
speed signaling requirement as well as low-speed device interface support. The HSMC interface
support JTAG, clock outputs and inputs, high speed LVDS and single-ended signaling. The HSMC
connector connects directly to the Cyclone IV E FPGA with 82 pins. Signals HSMC_SDA and
HSMC_SCLK share the same bus with the respected signals I2C_SDA and I2C_SCL of the
WM8731 audio ship and ADV7180 TV decoder chip.
consumption of the daughter card that connects to HSMC port.
Supplied Voltage
12V
3.3V
If the HSMC interface is utilized with design resources exceeding 50%, please notify our support
(support@terasic.com).
I2C_SDA. Because audio chip, TV decoder chip and HSMC share one I2C bus, therefore audio
and video chip won’t function correctly.
The voltage level of the I/O pins on the HSMC connector can be adjusted to 3.3V, 2.5V, 1.8V, or
1.5V using JP7 (The default setting is 2.5V, see
connected to Bank 5 & 6 of the FPGA and the VCCIO voltage (VCCIO5 & VCCIO6) of these
banks are controlled by the header JP7, users can use a jumper to select the input voltage of
VCCIO5 & VCCIO6 to 3.3V, 2.5V, 1.8V, and 1.5V to control the voltage level of the I/O pins.
Table 4-8
4
.
.
7
7
H
H
(1).Note the current levels indicated in
(2).If the HSMC loopback adapter is mounted, the I2C_SCL will be directly routed back to
i
i
g
g
lists the jumper settings of the JP7.
h
h
S
S
p
p
e
e
e
e
PIN_L2
PIN_L1
PIN_L3
PIN_L4
PIN_M1
PIN_M2
PIN_L5
PIN_L6
d
d
M
M
Table 4-7 Power Supply of the HSMC
e
e
z
z
z
z
a
a
n
n
LCD Data[2]
LCD Data[1]
LCD Data[0]
LCD Enable
LCD Read/Write Select, 0 = Write, 1 = Read
LCD Command/Data Select, 0 = Command, 1 = Data 3.3V
LCD Power ON/OFF
LCD Back Light ON/OFF
i
i
n
n
e
e
Max. Current Limit
1A
1.5A
C
C
Table 4-7
40
a
a
r
r
d
d
Figure
are based on 50% resource consumption.
Table 4-7
4-13). Because the HSMC I/Os are
shows the maximum power
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
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