P0071 Terasic Technologies Inc, P0071 Datasheet - Page 43

• Manufacturer Part Number: P0071
• Description: TPAD MULTIMEDIADEVELOPMENT KIT
• Manufacturer: Terasic Technologies Inc
• Series: tPAD, Cyclone®IVr

Specifications of P0071

• Main Purpose: Reference Design, Tablet
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: EP4CE115
• Primary Attributes: 8-Inch TFT LCD, LED Backlight
• Secondary Attributes: 5-Megapixel Digital Image Sensor
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Name
HSMC_CLKIN0
HSMC_CLKIN_N1
HSMC_CLKIN_N2
HSMC_CLKIN_P1
HSMC_CLKIN_P2
HSMC_CLKOUT0
HSMC_CLKOUT_N1 PIN_G24
HSMC_CLKOUT_N2 PIN_V24
HSMC_CLKOUT_P1 PIN_G23
HSMC_CLKOUT_P2 PIN_V23
HSMC_D[0]
HSMC_D[1]
HSMC_D[2]
HSMC_D[3]
HSMC_RX_D_N[0]
Figure 4-14 LVDS interface on HSMC connector and Cyclone IV E FPGA
FPGA Pin
No.
PIN_AH15
PIN_J28
PIN_Y28
PIN_J27
PIN_Y27
PIN_AD28
PIN_AE26 LVDS TX or CMOS I/O
PIN_AE28 LVDS RX or CMOS I/O
PIN_AE27 LVDS TX or CMOS I/O
PIN_AF27 LVDS RX or CMOS I/O
PIN_F25
Table 4-9 Pin Assignments for HSMC connector
Description
Dedicated clock input
LVDS RX or CMOS I/O or differential clock input
LVDS RX or CMOS I/O or differential clock input
LVDS RX or CMOS I/O or differential clock input
LVDS RX or CMOS I/O or differential clock input
Dedicated clock output
LVDS TX or CMOS I/O or differential clock input/output
LVDS TX or CMOS I/O or differential clock input/output
LVDS TX or CMOS I/O or differential clock input/output
LVDS TX or CMOS I/O or differential clock input/output
LVDS RX bit 0n or CMOS I/O
42
I/O Standard
Depending
on JP6
Depending
on JP7
Depending
on JP7
Depending
on JP7
Depending
on JP7
Depending
on JP7
Depending
on JP7
Depending
on JP7
Depending
on JP7
Depending
on JP7
Depending
on JP7
Depending
on JP7
Depending
on JP7
Depending
on JP7
Depending