P0307 Terasic Technologies Inc, P0307 Datasheet
P0307
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Terasic TRDB_LTM Digital Panel Package TRDB_LTM 4.3 Inch Digital Touch Panel Development Kit With complete reference design and source code for digital photo display and pattern generator using Altera DE2/ DE1 board Preliminary Version Document Version 1.22 9 NOV, 2007 ...
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Terasic TRDB_LTM Page Index CHAPTER 1 ABOUT THE KIT.....................................................................................................................................................1 1 .......................................................................................................................................................................1 IT ONTENTS 1-2 C LTM A ONNECTING TO THE LTERA 1 .......................................................................................................................................................................3 ETTING ELP CHAPTER 2 ARCHITECTURE OF THE LTM............................................................................................................................4 2-1 F ..............................................................................................................................................................................4 EATURES 2-2 ...
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Chapter The TRDB_LTM (LTM) Kit provides everything you need to develop applications using a digital touch panel on an Altera DE2/DE1 board. The kit contains complete reference designs and source code for implementing a photo viewer demonstration and a ...
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Connecting LTM to the Altera DE Board Please follow the two steps below to connect LTM to the Altera DE2/DE1 board: 1. Connect the IDE cable to the back of the LTM board, as shown in Figure 1.2 2. ...
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Figure 1.4 Connect the other end of IDE cable to the DE1 board’s expansion port (innermost expansion port) 1-3 Getting Help Here are some places to get help if you encounter any problem: Email to support@terasic.com Taiwan & China: +886-3-550-8800 ...
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Chapter Architecture of the LTM This chapter will illustrate the architecture of the LTM including device features and block diagram. The feature set of the LTM is listed below: 1. Equipped with Toppoly TD043MTEA1 active matrix color TFT LCD ...
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Block Diagram of the LTM The block diagram of the LTM is listed below: Figure 2.1 The block diagram of the LTM. The LTM consists of three major components: LCD touch panel module, AD converter, and 40-pin expansion header. ...
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Pin Description of the 40-pin Interface of LTM The pin description of the 40-pin connector follows: Pin Numbers ...
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VCC33 30 GND GREST 39 SCEN 40 SDA Table 2.1 The pin description of ...
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Chapter This chapter illustrates how to use the LTM including how to control the serial port interface of the LCD driver IC and AD converter. Also, the timing requirement of the synchronous signal and RGB data which are outputted ...
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SCEN input and starts data transfer. When setting instruction, the TPG110 inputs the setting values via SDA on the rising edge of input SCL. The first 6 bits (A5 ~ A0) specify the address ...
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Input timing of the LCD panel display function This section will describe the timing specification of the LCD synchronous signals and RGB data. To determine the sequencing and the timing of the image signals displayed on the LCD panel, ...
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Figure 3.2 LCD horizontal timing specification Parameter Symbol NCLK Frequency FNCLK t Horizontal valid data Horizontal Line h Min. t HSYNC Pulse Width Typ. hpw Max. t Hsync back porch hbp t Hsync front porch hfp t ...
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Figure 3.3 LCD vertical timing specification Parameter Symbol Vertical valid data Vertical period Min. VSYNC Pulse Width Typ. Max. Vertical back porch Vertical front porch Vertical blanking T DEN Enable Time Table 3.3 LCD vertical timing parameters Parameter NCLK period ...
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The serial interface of the AD converter This section will describe how to obtain the X/Y coordinates of the touch point from the AD converter. The LTM also equipped with an Analog Devices AD7843 touch screen digitizer chip. The ...
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Table 3.5 Control register bit function description. Figure 3.4 shows the typical operation of the serial interface of the ADC. The serial clock provides the conversion clock and also controls the transfer of information to and from the ADC. One ...
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Chapter This chapter illustrates how to exercise the LTM reference design provided with the kit. Users can follow the instructions in this chapter to build a 4.3 inch Ephoto demonstration and pattern generator using the DE2/DE1/DEN in 10 minutes. ...
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Loading Photos into the Flash Locate the project directory from the CD-ROM and follow the steps below: A: For Altera DE2 Board Quartus II Project Directory: DE2_Control_Panel_V1.04 FPGA Bitstream Used: DE2_USB_API.sof or DE2_USB_API.pof B: For Altera DE1 Board Quartus ...
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Figure 4.3. DE2 control panel window 6. Click on the “File Length” checkbox to indicate that you want to load the entire file 7. Click on the “Write a File to FLASH” bottom. When the Control Panel responds with the ...
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Configuring the Ephoto Demonstration Locate the project directory from the CD-ROM and follow the steps below: A: For Altera DE2 Board Quartus II Project Directory: DE2_LTM_Ephoto FPGA Bitstream Used: DE2_LTM_Ephoto.sof or DE2_LTM_Ephoto.pof B: For Altera DE1 Board Quartus II ...
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Figure 4.5. The connection setup for the Ephoto demonstration with DE1 board Touch here for the next photo Figure 4.6. The touch function of changing displayed photo Digital Panel Design Demonstration 19 Tuch here for the previous photo ...
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When users touch the LTM screen, the 7-segment displays "HEX6~HEX4" and "HEX2~HEX0" on the DE2 board will display the X and Y coordinates (in Hexadecimal format) of the touch point respectively indicates that the x and y coordinates of ...
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Figure 4.8 The block diagram of the Ephoto demonstration 4-5 Preprocessing the Desired Display Photo If users want to display their own photos on the LTM ,they can follow the steps below: 1. Prepar three 24 bit bmp format photos ...
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Figure 4.10 The photo format of the DE2_LTM_Ephoto/ DE1_LTM_Ephoto demonstration 22 Digital Panel Design Demonstration ...
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Configuring the Pattern Generator for DE2/DE1 Board Locate the project directory from the CD-ROM and follow the steps below: A: For Altera DE2 Board Quartus II Project Directory: DE2_LTM_Test FPGA Bitstream Used: DE2_LTM_Test.sof or DE2_LTM_Test.pof B: For Altera DE1 ...
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Figure 4.12. The connection setup for the pattern generator demo with DE1 board 2. Download the bitstream (DE2_LTM_Test/ DE1_LTM_Test) to the DE2/DE1 board 3. Press KEY0 on the DE2/DE1 board to reset the circuit 4. Touch the LTM screen to ...
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Configuring the Pattern Generator for DEN Board Locate the project directory from the CD-ROM and follow the steps below: Quartus II Project Directory: DEN_LTM_Test FPGA Bitstream Used: DEN_LTM_Test.pof 1. Ensure the connection is made correctly as shown in Figure ...
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Chapter 5-1 Absolute Maximum Ratings of the LCD Panel Module Item Logic Power Supply Voltage Input Signal Voltage Back Light Forward Current Operating Temperature Storage Temperature Chapter 5 Appendix Symbol Min Max Unit V 2.7 3 ...
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Power ON/OFF and Mode Change Sequence of the LCD Power on (low power or reset mode to normal mode) sequence: Power off (normal mode to low power mode) sequence : Panel Module 27 Appendix ...
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Register map of the LCD Driver IC Address Default Read/Write Description 0x00 0x00 R/W 0x01 0xC1 R 0x02 0x07 R/W 0x03 0x5F R/W 0x04 0x17 R/W 0x05 0x20 R/W 0x06 0x08 R/W 0x07 0x20 R/W 0x08 0x20 R/W 0x09 ...
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Register Definition of the LCD Driver IC R02h: R02[7:6]: Dot inversion ...
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R02[4] Function 0 Low pulse 1 High pulse R02[3]: Input clock latch data edge R02[5] Function 0 Latch data at NCLK falling edge 1 Latch data at NCLK rising edge R02[2:0]: Resolution selection R02[2: ...
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R03[3]: PWM output ON/OFF R03[3] Function 0 PWM disable 1 PWM enable R03[2]: VGL pump output ON/OFF R03[2] Function 0 VGL pump disable 1 VGL pump enable R03[1]: CP_CLK output ON/OFF R03[1] Function 0 CP_CLK disable 1 ...
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H(~64KHz 1/4 * H(~128KHz) R04[1]: Vertical reverse function R04[1] Function 0 Reverse (CSV=L) 1 Normal (CSV=H) R04[0]: Horizontal reverse function R04[0] Function 0 Reverse 1 Normal R05h: R05[5:0]: Horizontal display position shift for SYNC ...
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R07h~R0Ah: R07[5:0]: CKH high pulse width adjustment. Set 0x20 for normal operation. ...
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R0Ch: R0C[5:0]: G Gain of Contrast R0C[5:0] G Gain of Contrast 0x00 0x20 0x3F R0Dh: R0D[5:0]: B Gain of Contrast R0D[5:0] B Gain of Contrast 0x00 0x20 0x3F R0Eh: R0E[5:0]: R Offset of Brightness R0E[5:0] R Offset of ...
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R10h: R10[5:0]: B Offset of Brightness R10[5:0] B Offset of Brightness 0x00 0x10 0x3F R11h ~ R1Fh: Gamma Correction The gamma correction is done by 11-segment piecewise linear interpolation. The 11 segments are defined with 12 register values for level ...
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Level R20[3:0] defines positive polarity DAC reference voltage for code 00H 0x2 R20[3:0] 0x0 0x1 0x3 (Default) Gamma 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 Level R21 : Voltage range for ...
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V1.0 V1.1 V1.2 V1.21 V1.22 5-6Always Visit LTM Webpage for New Applications We will continually provide interesting examples and labs on our LTM webpage. Please visit www.altera.com Initial Version (Preliminary) Edit appendix. Edit Ch3 and Ch4. Edit Figure 4.1, Figure ...