P0071 Terasic Technologies Inc, P0071 Datasheet - Page 48
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P0071
Manufacturer Part Number
P0071
Description
TPAD MULTIMEDIADEVELOPMENT KIT
Manufacturer
Terasic Technologies Inc
Series
tPAD, Cyclone®IVr
Specifications of P0071
Main Purpose
Reference Design, Tablet
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
EP4CE115
Primary Attributes
8-Inch TFT LCD, LED Backlight
Secondary Attributes
5-Megapixel Digital Image Sensor
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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The voltage level of the I/O pins on the expansion headers can be adjusted to 3.3V, 2.5V, 1.8V, or
1.5V using JP6 (The default value is 3.3V, see
connected to Bank 4 of the FPGA and the VCCIO voltage (VCCIO4) of this bank is controlled by
the header JP6, users can use a jumper to select the input voltage of VCCIO4 to 3.3V, 2.5V, 1.8V,
and 1.5V to control the voltage level of the I/O pins.
The pin-outs of the JP6 appear in
JP6 Jumper Settings
Short Pins 1 and 2
Short Pins 3 and 4
Short Pins 5 and 6
Short Pins 7 and 8
Table 4-11 Voltage Level Setting of the Expansion Headers Using JP6
Figure 4-17 GPIO VCCIO supply voltage setting header
Supplied Voltage to VCCIO4
1.5V
1.8V
2.5V
3.3V
Figure
4-17.
47
Figure
Table 4-11
4-17). Because the expansion I/Os are
IO Voltage of Expansion Headers (JP5)
1.5V
1.8V
2.5V
3.3V (Default)
lists the jumper settings of the JP6.
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