IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 54

• Manufacturer Part Number: IPR-POSPHY4
• Description: IP CORE Renewal Of IP-POSPHY4
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–14
Table 4–3. SPI-4.2 Protocol Error Handling (Part 1 of 3)
POS-PHY Level 4 MegaCore Function User Guide
Protocol error
Start-of-packet spacing
violation (SOP8)
Start of burst error
(SOB)
Training pattern error
8N boundary error
(8N_ERR)
SPI-4.2 Protocol Errors
Error
The receiver MegaCore function decodes the control words from the incoming SPI-4.2
interface and ensures that they follow the state machine shown in Fig. 6.2. Data Path
State Diagram of the SPI-4.2 Specification, and ensures that there are no other errors.
Table 4–3
A transition on the receiver data path that does not follow
Fig. 6.2. Data Path State Diagram of the SPI-4.2
Specification.
The SPI-4.2 specification states that SOP control words
should not be less than 8 cycles apart.
Data or training data is received without a payload control
word.
Training pattern errors (err_rd_tp) occur when one of the
following conditions occur:
■
■
■
■
■
■
■
A burst that is neither a multiple of 16 bytes, nor an EOP.
Training control portion is too short.
Training control portion is too long.
Training data portion is too short.
Training data portion is too long.
Training control word is followed by something other
than another training control word or training data
word.
Malformed data bus during a data or control word.
Missing IDLE before training pattern begins. (The IDLE
can be an EOP).
summarizes the SPI-4.2 protocol errors.
Condition
(Note
1),
(2)
Chapter 4: Functional Description—Receiver
■
■
■
■
■
■
■
■
■
■
■
■
Assert err_rd_pr for one clock
cycle.
Asserts err_rd_sop8 for one
clock cycle. When this happens,
the data is not affected.
Assert err_rd_sob for one
cycle.
Data is dropped until a proper
payload control word is received.
Assert err_rd_tp at the end of
the training pattern.
Channel aligner may not lock.
Some training pattern errors may
result in successive assertions of
the err_rd_tp interrupt (for
example, Training Control portion
> 10 cycles).
Assert err_rd_eightn for one
clock cycle.
Packet is marked as errored.
Consider error as a missing EOP.
Cleanly terminate packet
internally as an EOP-Abort.
Process subsequent bursts as
per missing SOP.
December 2010 Altera Corporation
Response
Error Flagging and Handling
(3)