IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 19

• Manufacturer Part Number: IPR-POSPHY4
• Description: IP CORE Renewal Of IP-POSPHY4
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Simulate the Design
Table 2–1. Generated Files (Part 2 of 2)
Simulate the Design
December 2010 Altera Corporation
<variation name>_tb.v
<variation name>.bsf
<variation name>.html
<variation name>.ppf
<variation name>.sdc
<variation name>.v or .vhd
<variation_name>.vo or .vho
f
1
File
11. After you review the generation report, click Exit to close IP Toolbench and click
You can now integrate your custom MegaCore function variation into your design
and simulate and compile.
Constraints are automatically set by the MegaWizard Plug-In Manager.
You can simulate your design using the IP Toolbench-generated VHDL and Verilog
HDL IP functional simulation models.
For more information on IP functional simulation models, including NativeLink, refer
to
Simulation Tools
“Simulate the Design” on page 2–3
Yes on the Quartus II IP Files message.
1
The Quartus II IP File (.qip) is a file generated by the MegaWizard interface
or SOPC Builder that contains information about a generated MegaCore
function. You are prompted to add this .qip file to the current Quartus II
project at the time of file generation. In most cases, the .qip file contains all
of the necessary assignments and information required to process the
MegaCore function or system in the Quartus II compiler. Generally, a single
.qip file is generated for each MegaCore function and for each SOPC
Builder system. However, some more complex SOPC Builder components
generate a separate .qip file, so the system .qip file references the
component .qip file.
chapter in volume 3 of the Quartus II Handbook.
A Verilog HDL testbench for the requested parameterization.
Quartus II symbol file for the MegaCore function variation. You can use this file
in the Quartus II block diagram editor.
The MegaCore function report file.
XML file that describes the MegaCore pin attributes to the Quartus II Pin
Planner. MegaCore pin attributes include pin direction, location, I/O standard
assignments, and drive strength.
TimeQuest SDC constraint settings file for timing analysis. Use this file to
specify constraints required for TimeQuest analysis.
A MegaCore function variation file, which defines a Verilog HDL top-level
description of the custom MegaCore function. Instantiate the entity defined by
this file inside of your design. Include this file when compiling your design in the
Quartus II software.
Verilog HDL IP functional simulation model.
and the
Description
Simulating Altera IP in Third-Party
POS-PHY Level 4 MegaCore Function User Guide
2–3