IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 112

• Manufacturer Part Number: IPR-POSPHY4
• Description: IP CORE Renewal Of IP-POSPHY4
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

A–2
Table A–1. Start-Up Sequence (Part 1 of 2)
POS-PHY Level 4 MegaCore Function User Guide
Event
1
2a
2b
3
3
4
5a
Power Up
Release PLL
areset
Wait for other clock
to stabilize.
Release MegaCore
function reset
MegaCore function
Configuration
(Optional)
—
Trained—DPA
variations of
receiver MegaCore
functions
Description
1
For a 32-bit transmitter MegaCore function, no PLLs are used so the
ctl_tx_pll_areset and stat_rx_pll_locked signals do not exist.
Assert ctl_rx_pll_areset and
rxreset_n.
The receiver MegaCore function sends
framing pattern('b11) on rstat[1:0].
Release receiver PLL reset
(ctl_rx_pll_areset) after rdclk
stabilizes (timed). Wait for the receiver PLL to
lock (stat_rx_pll_locked).
Wait for all the other clocks (aN_arxclk,
rxsys_clk and rav_clk) to be stable.
Wait for at least 4 clock cycles of the
receiver’s slowest clock, then release the
receiver reset (rxreset_n).
If MegaCore function configuration needs to
be performed, assert ctl_ry_rsfrm to
disable the status finite state machine (FSM)
from transmitting valid status information.
If Asymmetric Port Support and/or Hitless
B/W Reprovisioning is turned on, set up the
calendar parameters using the Avalon
Memory-Mapped (Avalon-MM) interface
(refer to
4.2 Calendar via the Avalon Memory-Mapped
Interface
function configuration is complete deassert
ctl_ry_rsfrm. All the MegaCore function
parameters (signals that start with ctl_)
must be stable before releasing
ctl_ry_rsfrm.
The MegaCore function may transmit a valid
status frame if the training is complete.
DPA circuitry locks onto the training pattern
(1 to approximately 1,000 training repetitions
are required). Stratix IV, Stratix III, Stratix II,
and Stratix GX devices indicate altlvds DPA
has locked by asserting
stat_rd_dpa_lvds_locked. DPA channel
aligner lock is indicated by
stat_rd_dpa_locked.
Receiver MegaCore Function
Appendix E, Programming the SPI-
for details). Once the MegaCore
®
Assert ctl_tx_pll_areset and
txreset_n.
—
After trefclk stabilizes, deassert the
transmitter PLL reset
(ctl_tx_pll_areset).
Wait for the transmitter PLL to lock
(stat_tx_pll_locked). Depending on the
source of trefclk, you can deassert the PLL
reset by observing a PLL locked signal,
waiting for a fixed amount of time, or both.
Wait for all the clocks (aN_atxclk,
txsys_clk and tav_clk) to be stable.
Wait for at least 4 clock cycles of the
transmitter’s slowest clock, then release the
transmitter reset (txreset_n).
As soon as reset is released, the MegaCore
function sends a continuous training pattern.
If MegaCore function configuration needs to
be performed, assert ctl_ts_rsfrm to
prevent the MegaCore function from
attempting to frame, and force it to send a
continuous training pattern.
If Asymmetric Port Support and/or Hitless
B/W Reprovisioning is turned on, set up the
calendar parameters using the Avalon-MM
interface (refer to
the SPI-4.2 Calendar via the Avalon Memory-
Mapped Interface
MegaCore function configuration is complete
deassert ctl_ts_rsfrm. All the MegaCore
function parameters (signal that start with
ctl_) must be stable before releasing
ctl_ts_rsfrm.
The status framer searches for a valid status
frame.
—
Transmitter MegaCore Function
December 2010 Altera Corporation
Appendix E, Programming
for details). Once the
Appendix A: Start-Up Sequence