IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 108

• Manufacturer Part Number: IPR-POSPHY4
• Description: IP CORE Renewal Of IP-POSPHY4
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–8
Table 6–6. Packet Format
POS-PHY Level 4 MegaCore Function User Guide
Header byte
Extra length byte {size[16:0]}
Number byte
Payload bytes
Packet Byte
{0,0,len[5:1],ext}
{N[7:0] ^ port_num}
{N++^ port_num}
When an error is asserted on the Atlantic interface with a valid EOP, and an end of
packet abort message is sent to the SPI-4.2 interface, it is not counted as an error in the
data and does not cause the testbench to fail.
The packet tasks for each port are called in parallel via a fork or join statement.
Arbitration is handled in the data generator module and varies for each buffer mode.
■
■
The packets have lengths defined in the top-level testbench and follow the format in
Table
The testbench concludes by checking that all of the packets have been received. In
addition, it checks that the POS-PHY Level 4 packet receiver (packet analyzer
module) has not detected any errors in the received packets. If no error has been
detected, and all packets have been received, the testbench issues a message stating
that the simulation was successful.
If an error has been detected, a message states that the testbench has failed. If not all
packets have been detected, a message states that the testbench is incomplete. The
tb.exp_chk_cnt variable determines the number of checks done to ensure
completeness of the testbench. For each port tested, one completeness check is done.
In addition, a preliminary check is done to make sure synchronization is complete,
and a final check is done for the conclusion of the testbench.
Optionally, the testbench can test backpressure on the SPI-4.2 interface. When the
backpressure variable is defined, backpressure is generated on one or more ports, by
first setting the status for the appropriate ports to satisfied. This action informs the
POS-PHY Level 4 transmitter MegaCore function to not send data to those ports
(specific reaction to backpressure depends on the variation selected). The data
generator continues to write to the buffers until the Atlantic aN_arxdav or aN_atxdav
signal goes high, indicating that the buffer is nearly full. The testbench then turns the
status for the satisfied ports back to starving or hungry. The POS-PHY Level 4
For individual buffers variations, the packets can be written in parallel.
For shared buffer with embedded addressing variations, the arbiter selects each
port in a round-robin fashion, switching to the next port at a fixed interval.
6–6.
Format
Contains info about the packet. len is the length of the packet if the
length can be encoded in six bits. If the length is beyond 32 bits, ext is
set to indicate that the next byte in the packet contains the length
information.
If ext is 1, the extended expected packet size shows the length of the
packet including the header (size > 16 bytes) (optional).
Packet number (packet number begins at 'h01 and is incremented by
one for each packet) XORed with the port number.
The following bytes in the packet are incremented by one and XORed with
the port number.
Description
December 2010 Altera Corporation
Transmitter Testbench Description
Chapter 6: Testbench