IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 44

• Manufacturer Part Number: IPR-POSPHY4
• Description: IP CORE Renewal Of IP-POSPHY4
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–4
Figure 4–2. DPA and Channel Aligner Block Diagram
Notes to
(1) The width of the data path for the data_out, data_out_algn, and data:2 signals depends on the deserialization factor.
(2) Exists only for Stratix GX devices, if the internal data path width is 64 bits.
(3) The stat_rd_dpa_lvds_locked signal does not exist in the altlvds block for Stratix GX devices. It is tied to a logic 1 inside the receiver
POS-PHY Level 4 MegaCore Function User Guide
MegaCore function.
Figure
4–2:
ALTLVDS_RX Megafunction
The ALTLVDS_RX megafunction always performs deserialization on the input rdat
and rctl high-speed LVDS signals, and divides the DDR rdclk to produce a slower
rdint_clk.
When DPA is enabled in the POS-PHY Level 4 MegaCore function, the ALTLVDS_RX
megafunction has two other features enabled: DPA and bit slip. DPA with respect to
ALTLVDS has a different meaning than DPA with respect to the POS-PHY Level 4
MegaCore function. After DPA resets, the ALTLVDS DPA feature tolerates only a
small amount of change to the channel-to-channel skew, which compensates for the
very small amounts of change in channel-to-channel skew that may occur due to
voltage and temperature shifts during system operation. A change in channel-channel
skew that is greater than the bit-time tolerance causes one or more of the internal
deskew FIFO buffers to underflow or overflow, which the POS-PHY Level 4
MegaCore function detects only as DIP-4 errors. You must use the DIP-4 thresholds
and stat_rd_dip4_oos to trigger the DPA reset by asserting
ctl_rd_dpa_force_unlock.
The stat_rd_dpa_lvds_locked signal indicates when the DPA cannot stay locked
either because of a lack of transitions on the channel, or because of rapid changes in
skew. The DPA run length is 6,400 UI for Stratix III, Stratix II, and Stratix GX devices.
If the traffic on the SPI-4.2 interface is very sparse, periodic training patterns may be
required.
To compensate for large amounts of static channel-to-channel skew, the POS-PHY
Level 4 MegaCore function channel aligner state machine uses the bit slip feature (the
channel align or data realignment) of the ALTLVDS_RX megafunction.
The POS-PHY Level 4 MegaCore function automatically configures and includes the
ALTLVDS_RX megafunction.
Channel Aligner
The DPA feature of the ALTLVDS_RX megafunction provides parallel data sampled
correctly and aligned to a single clock. As it does not use a data pattern, it cannot
compensate for more than one bit time of channel-to-channel skew which may exist
due to trace length mismatches.
The channel aligner sub-block uses the SPI-4.2 training pattern to align the parallel
data. Alignment is done once at start-up, and then only when requested by asserting
the ctl_rd_dpa_force_unlock signal. The channel aligner state machine begins the
alignment process once the ctl_rd_dpa_force_unlock signal is deasserted and the
altlvds_rx megafunction asserts the stat_rd_dpa_lvds_locked signal (high). It then
pulses the bits of the align[16:0] signal channel by channel until all channels are
Chapter 4: Functional Description—Receiver
December 2010 Altera Corporation
Block Description