EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 785

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

IDEMDMADataIn
IDEUDMADataOut
DS785UM1
31
15
31
15
Bit Descriptions:
Address:
Default:
Definition:
Bit Descriptions:
Address:
Default:
Definition:
30
14
30
14
29
13
29
13
28
12
28
12
DMA controller. A write by the host during MDMA data-out operation will
erroneously interfere with the MDMA state machine. Any read will return zero.
IDEDD:
0x800A_001C - Read Only (should be read by the DMA controller only)
0x0000_0000
In MDMA data-in operations, this register contains the data in the input buffer
just transferred from the device. The data is read from this register by the DMA
controller. This register should only be addressed and read by the DMA
controller. A read by the host during MDMA data-in operation will erroneously
interfere with the MDMA state machine. Any write is ignored.
IDEDD:
0x800A_0020 - Write Only (should be written by the DMA controller only)
0x0000_0000
In UDMA data-out operations, this register contains the data at the tail of the
output buffer to be written by the DMA controller. This register should only be
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
IDE output data in the output buffer in MDMA mode.
IDE input data in the input buffer in MDMA mode.
24
24
8
8
IDEDD
IDEDD
IDEDD
IDEDD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
EP93xx User’s Guide
18
18
2
2
IDE Interface
17
17
1
1
27-15
16
16
0
0
27