EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 448

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

11
11-8
Universal Serial Bus Host Controller
EP93xx User’s Guide
11.2.4 Host Controller Responsibilities
11.2.4.1 USB States
11.2.4.2 Frame Management
11.2.4.3 List Processing
This section summarizes the Host Controller (HC) responsibilities.
There are four USB states defined in OpenHCI: UsbOperational, UsbReset, UsbSuspend,
and UsbResume. The Host Controller puts the USB bus in the proper operating mode for
each state.
The Host Controller keeps track of the current frame counter and the frame period. At the
beginning of each frame, the Host Controller generates the Start of Frame (SOF) packet on
the USB bus and updates the frame count value in system memory. The Host Controller also
determines if enough time remains in the frame to send the next data packet.
The Host Controller operates on the Endpoint Descriptors and Transfer Descriptors
enqueued by the Host Controller Driver.
For interrupt and isochronous transfers, the Host Controller begins at the Interrupt Endpoint
Descriptor head pointer for the current frame. The list is traversed sequentially until one
packet transfer from the first Transfer Descriptor of all interrupt and isochronous Endpoint
Descriptors scheduled in the current frame is attempted.
For bulk and control transfers, the Host Controller begins in the respective list where it last left
off. When the Host Controller reaches the end of a list, it loads the value from the head
pointer and continues processing. The Host Controller processes n control transfers to 1 bulk
transfer where the value of n is set by the Host Controller Driver.
When a Transfer Descriptor completes, either successfully or due to an error condition, the
Host Controller moves it to the Done Queue. Enqueuing on the Done Queue occurs by
placing the most recently completed Transfer Descriptor at the head of the queue. The Done
Queue is transferred periodically from the Host Controller to the Host Controller Driver via the
HCCA.
Copyright 2007 Cirrus Logic
DS785UM1