EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 389

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

RXStsThrshld
DS785UM1
31
15
Address:
Suggested Value:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
TDST:
0x8001_00D8 - Read/Write
0x0004_0002
0x0000_0000
Unchanged
Receive Status Threshold register. The receive status threshold are used to
set a limit on the amount of receive status which is held in the receive status
FIFO before a bus request will be scheduled. When the number of words in
the FIFO exceeds the threshold value, the Descriptor Processor will schedule
a bus request to transfer status. The actual posting of the bus request may be
delayed due to lack of resources in the MAC, such as the RXStsEnq register
being equal to zero. The lower two bits of the thresholds are always zero.
RSVD:
RSHT:
RSST:
27
11
RSVD
RSVD
26
10
Copyright 2007 Cirrus Logic
25
9
Transmit Data Soft Threshold. The hard and soft threshold
work in exactly the same manner except one. The soft
threshold will not cause a bus request to be made if the
bus is currently in use, but only when it is deemed to be
idle (no transfers for four AHB clocks). The hard threshold
takes effect immediately regardless of the state of the bus.
This operation allows for more efficient use of the AHB bus
by allowing smaller transfers to take place when the bus is
lightly loaded and requesting larger transfers only when
the bus is more heavily loaded.
Reserved. Unknown During Read.
Receive Status Hard Threshold.
Receive Status Soft Threshold.
24
8
23
7
22
6
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
RSHT
RSST
19
3
EP93xx User’s Guide
18
2
17
0
1
0
16
9-87
0
0
0
9