EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 546

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

14
UART1IntIDIntClr
14-24
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
CTS:
0x808C_001C - Read/Write
0x0000_0000
UART Interrupt Identification and Interrupt Clear Register.
RSVD:
RTIS:
TIS:
RIS:
MIS:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
Clear To Send status. This bit is the complement of the
UART clear to send (nUARTCTS) modem status input.
That is, the bit is 1 when the modem status input is 0.
Reserved. Unknown During Read.
Receive Timeout Interrupt Status. This bit is set to 1 if the
UARTRTINTR receive timeout interrupt is asserted. This
bit is cleared when the receive FIFO is empty or the
receive line goes active.
Transmit Interrupt Status.
1 - The UARTTXINTR transmit interrupt is asserted, which
occurs when the transmit FIFO is not full.
0 - The transmit FIFO is full.
Receive Interrupt Status.
1 - The UARTRXINTR receive interrupt is asserted, which
occurs when the receive FIFO is not empty.
0 - The receive FIFO is empty.
Modem Interrupt Status. This bit is set to 1 if the
UARTMSINTR modem status interrupt is asserted. This
bit is cleared by writing any value to this register.
24
8
RSVD
23
7
22
6
21
5
20
4
RTIS
19
3
TIS
18
2
RIS
17
1
DS785UM1
MIS
16
0