EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 133

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

DS785UM1
There are some limitations of each clock. FCLK must be <=200 MHz, HCLK<=100 MHz and
PCLK<=50 MHz and FCLK >= HCLK > PCLK. Refer to register,
the detailed configuration information regarding the divider bit fields.
MAX = 100 MHz
External Clock
PCLK Divide = 1, 2, 4, 8
HCLK
Div
PCLK
Div
Figure 5-3. Bus Clock Generation
Copyright 2007 Cirrus Logic
PLL1
FCLK
Div
MAX = 500 MHz
MAX = 250 MHz
MAX = 50 MHz
For 2nd stage dividers:
HCLK Divide = 1, 2, 4, 5, 6,
FCLK Divide = 1, 2, 4, 8, 16
8, 16, 32
“ClkSet1” on page
FCLK
HCLK
PCLK
EP93xx User’s Guide
System Controller
5-18, for
5-7
5