EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 143

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

Standby and Halt
TEOI
DS785UM1
31
15
31
15
Address:
Definition:
Bit Descriptions:
Address:
Definition:
Bit Descriptions:
Note: When a read is performed to the Standby location, it must be immediately followed by 5
30
14
30
14
NOP instructions. This is needed to flush the instruction pipeline in the ARM920T core.
Writes to these locations have no effect.
29
13
29
13
28
12
28
12
Standby - 0x8093_000C - Read Only
Halt - 0x8093_0008 - Read Only
The Standby and Halt registers allow entry into the power saving modes. A
read to the Halt location will initiate a request for the system to enter Halt
mode, if the SHena bit is set in the DeviceCfg register in Syscon. Likewise a
read to Standby will request entry into Standby only when the SHena bit is set.
RSVD:
0x8093_0018 - Write
Writing to the TEOI location will clear the periodic Watchdog expired interrupt
(WEINT) and the 64 Hz TICK interrupt (TINT). Any data written to the register
triggers the clearing.
RSVD:
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
There are no readable bits in this register.
There are no readable bits in this register.
24
24
8
8
RSVD
RSVD
RSVD
RSVD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
EP93xx User’s Guide
System Controller
18
18
2
2
17
17
1
1
16
16
5-17
0
0
5