AU80610004671AAS LBMH Intel, AU80610004671AAS LBMH Datasheet - Page 74

• Manufacturer Part Number: AU80610004671AAS LBMH
• Description: MPU, ATOM PROCESSOR, D410, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D400r

Specifications of AU80610004671AAS LBMH

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.6.10
74
C0CYCTRKWR - Channel 0 CYCTRK WR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 0 CYCTRK WR Registers.
15:12
12:9
11:8
8:0
7:4
3:0
Bit
Bit
Acces
Access
RW
RW
RW
RW
RW
RW
s
Defau
Value
00000000
0h
0h
0h
0h
lt
Default
Value
0h
0b
RST/
PWR
Core
Core
Core
Core
RST/
PWR
Core
Core
0/0/0/MCHBAR
256-257h
0000h
16 bits
RW;
ACT To Write Delay (C0sd_cr_act_wr):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between the ACT
and WRITE commands to the same rank-
bank. Corresponds to tRCD_wr at DDR Spec.
Same Rank Write To Write Delayed
(C0sd_cr_wrsr_wr):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between two
WRITE commands to the same rank.
Different Rank Write to Write Delay
(C0sd_cr_wrdr_wr):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between two
WRITE commands to different ranks. Corresponds
to tWR_WR at DDR Spec.
READ To WRTE Delay (C0sd_cr_rd_wr):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between the READ
and WRITE commands. Corresponds to tRD_WR.
ALLPRE to ACT Delay
(C0sd0_cr_preall_act):
From the launch of a precharged command
wait for these many # of MCLKs before
launching a activate command. Corresponds to
tPALL_RP.
REF to ACT Delayed (C0sd_cr_rfsh_act):
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between REF and ACT commands to the same
rank. Corresponds to tRFC at DDR Spec.
Processor Configuration Registers
Description
Description
Datasheet