AU80610004671AAS LBMH Intel, AU80610004671AAS LBMH Datasheet - Page 72

• Manufacturer Part Number: AU80610004671AAS LBMH
• Description: MPU, ATOM PROCESSOR, D410, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D400r

Specifications of AU80610004671AAS LBMH

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.6.7
1.6.8
72
C0DRA23 - Channel 0 DRAM Rank 2, 3 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
See C0DRA01
C0CYCTRKPCHG - Channel 0 CYCTRK PCHG
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 0 CYCTRK Precharge Registers.
15:11
15:8
10:6
7:0
5:2
Bit
Bit
Access
Access
RW/L
RW/L
RW
RW
RO
Default
Default
00000b
00000b
Value
Value
0000b
00h
00h
/PWR
RST/
PWR
Core
Core
Core
Core
Core
RST
0/0/0/MCHBAR
20A-20Bh
0000h
16 bits
0/0/0/MCHBAR
250-251h
0000h
16 bits
RW/L;
RO; RW;
See table in register description for
programming
See table in register description for
programming
Channel 0 DRAM Rank-3 Attributes
(C0DRA3):
This register defines DRAM page size/number-
of-banks for rank3 for given channel
Channel 0 DRAM Rank-2 Attributes
(C0DRA2):
This register defines DRAM page size/number-
of-banks for rank2 for given channel
Reserved ():
Reserved.
Write To PRE Delayed (C0sd_cr_wr_pchg):
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between the WRITE and PRE commands to the
same rank-bank. Corresponds to tWR at DDR
Specification.
READ To PRE Delayed (C0sd_cr_rd_pchg):
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between the READ and PRE commands to the
same rank-bank.
Processor Configuration Registers
Description
Description
Datasheet