AU80610004671AAS LBMH Intel, AU80610004671AAS LBMH Datasheet - Page 73

• Manufacturer Part Number: AU80610004671AAS LBMH
• Description: MPU, ATOM PROCESSOR, D410, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D400r

Specifications of AU80610004671AAS LBMH

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.6.9
Datasheet
C0CYCTRKACT - Channel 0 CYCTRK ACT
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 0 CYCTRK Activate Registers.
31:28
27:22
20:17
16:13
1:0
Bit
Bit
21
Access
Access
RW
RW
RW
RW
RW
RO
000000b
Default
Default
0000b
0000b
Value
Value
00b
0h
0b
/PWR
RST/
PWR
Core
Core
Core
Core
Core
Core
RST
0/0/0/MCHBAR
252-255h
00000000h
32 bits
RW; RO;
PRE To PRE Delayed (C0sd_cr_pchg_pchg):
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between two PRE commands to the same rank.
RESERVED () (RESERVED ())
ACT Window Count
(C0sd_cr_act_windowcnt):
This configuration register indicates the window
duration (in DRAM clocks) during which the
controller counts the # of activate commands
which are launched to a particular rank. If the
number of activate commands launched within
this window is greater than 4, then a check is
implemented to block launch of further
activates to this rank for the rest of the
duration of this window.
Max ACT Check Disable
(C0sd_cr_maxact_dischk):
This configuration register disenables the
check, which ensures that there are no more
than four activates to a particular rank in a
given window.
ACT to ACT Delayed (C0sd_cr_act_act[):
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between two ACT commands to the same rank.
Corresponds to tRRD at DDR Spec.
PRE to ACT Delayed (C0sd_cr_pre_act):
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between the PRE and ACT commands to the
same rank-bank:12:9R/W0000bPRE-ALL to
ACT Delayed (C0sd_cr_preall_act):This
configuration register indicates the minimum
allowed spacing (in DRAM clocks) between the
PRE-ALL and ACT commands to the same
rank. Corresponds to tRP at DDR Spec.
Description
Description
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