AU80610004671AAS LBMH Intel, AU80610004671AAS LBMH Datasheet - Page 44

• Manufacturer Part Number: AU80610004671AAS LBMH
• Description: MPU, ATOM PROCESSOR, D410, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D400r

Specifications of AU80610004671AAS LBMH

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.17
1.5.18
44
DMIBAR - Root Complex Register Range Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the CPU Uncore. There is no physical memory within this 4KB window
that can be addressed. The 4KB reserved by this register does not alias to any PCI 2.3
compliant memory mapped space. On reset, the Root Complex configuration space is
disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0]
PAM0 - Programmable Attribute Map 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the read, write, and shadowing attributes of the BIOS area from
0F0000h- 0FFFFFh. The CPU Uncore allows programmable memory attributes on 13
Legacy memory segments of various sizes in the 768 KB to 1 MB address range.
Seven Programmable Attribute Map (PAM) Registers are used to support these
features. Cacheability of these areas is controlled via the MTRR registers in the P6
processor. Two bits are used to specify memory attributes for each memory segment.
These bits apply to both host accesses and PCI initiator accesses to the PAM areas.
These attributes are:
63:36
35:12
11:1
Bit
0
Access
RW/L
RW/L
RO
RO
0000000h
000000h
Default
Value
000h
0b
RST/
PWR
Core
Core
Core
Core
0/0/0/PCI
68-6Fh
0000000000000000h
64 bits
0/0/0/PCI
90h
00h
8 bits
RW/L; RO;
RO; RW/L;
Reserved (DMIBAR_rsv)
DMI Base Address (DMIBAR):
base address DMI configuration space. BIOS
will program this register resulting in a base
address for a 4KB block of contiguous memory
address space. This register ensures that a
naturally aligned 4KB space is allocated within
the first 64GB of addressable memory space.
System Software uses this base address to
program the DMI register set.
Reserved ()
DMIBAR Enable (DMIBAREN):
0: DMIBAR is disabled and does not claim any
memory
1: DMIBAR memory mapped accesses are
claimed and decoded appropriately
This field corresponds to bits 35 to 12 of the
Processor Configuration Registers
Description
Datasheet