AU80610004671AAS LBMH Intel, AU80610004671AAS LBMH Datasheet - Page 53
AU80610004671AAS LBMH
Manufacturer Part Number
AU80610004671AAS LBMH
Description
MPU, ATOM PROCESSOR, D410, FC-BGA8
Manufacturer
Intel
Series
ATOM - D400r
Datasheet
1.AU80610004392AAS_LBLA.pdf
(153 pages)
Specifications of AU80610004671AAS LBMH
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Operating Temperature Range
0°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Processor Configuration Registers
1.5.27
1.5.28
Datasheet
REMAPLIMIT - Remap Limit Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
SMRAM - System Management RAM Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit
is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
15:10
9:0
Bit
Bit
7
6
5
Access
Access
RW/L
RW/L
RW
RO
RO
000000b
Default
Default
Value
Value
000h
0b
0b
0b
RST/
RST/
PWR
PWR
Core
Core
Core
Core
Core
0/0/0/PCI
9A-9Bh
0000h
16 bits
0/0/0/PCI
9Dh
02h
8 bits
RO; RW/L;
RO; RW/L; RW; RW/L/K;
When the value in this register is less than the
value programmed into the Remap Base
register, the Remap window is disabled.
Reserved ()
Remap Limit Address [35:26] (REMAPLMT):
boundary of the Remap window. The Remap
window is inclusive of this address. In the
decoder A[25:0] of the remap limit address are
assumed to be F's. Thus the top of the defined
range will be one less than a 64MB boundary.
Reserved ()
SMM Space Open (D_OPEN):
space DRAM is made visible even when SMM
decode is not active. This is intended to help
BIOS initialize SMM space. Software should
ensure that D_OPEN=1 and D_CLS=1 are not
set at the same time.
SMM Space Closed (D_CLS):
accessible to data references, even if SMM
decode is active. Code references may still
access SMM space DRAM. This will allow SMM
software to reference through SMM space to
The value in this register defines the upper
When D_OPEN=1 and D_LCK=0, the SMM
When D_CLS = 1 SMM space DRAM is not
Description
Description
53
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