AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 457

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

24 Analog Comparator .............................................................................. 310
25 Analog to Digital Converter - ADC ...................................................... 313
26 JTAG Interface and On-chip Debug System ...................................... 332
27 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 338
7593K–AVR–11/09
23.9 Remote Wake-Up detection ..............................................................................293
23.10 USB Pipe Reset ...............................................................................................293
23.11 Pipe Data Access ............................................................................................293
23.12 Control Pipe management ...............................................................................294
23.13 OUT Pipe management ...................................................................................294
23.14 IN Pipe management .......................................................................................295
23.15 Interrupt system ...............................................................................................296
23.16 Registers .........................................................................................................297
24.1 Analog Comparator Multiplexed Input ...............................................................312
25.1 Features ............................................................................................................313
25.2 Operation ...........................................................................................................314
25.3 Starting a Conversion ........................................................................................315
25.4 Prescaling and Conversion Timing ....................................................................316
25.5 Changing Channel or Reference Selection .......................................................319
25.6 ADC Noise Canceler .........................................................................................320
25.7 ADC Conversion Result .....................................................................................324
25.8 ADC Register Description ..................................................................................326
26.1 Overview ............................................................................................................332
26.2 Test Access Port – TAP ....................................................................................332
26.3 TAP Controller ...................................................................................................334
26.4 Using the Boundary-scan Chain ........................................................................335
26.5 Using the On-chip Debug System .....................................................................335
26.6 On-chip Debug Specific JTAG Instructions .......................................................336
26.7 On-chip Debug Related Register in I/O Memory ...............................................337
26.8 Using the JTAG Programming Capabilities .......................................................337
26.9 Bibliography .......................................................................................................337
27.1 Features ............................................................................................................338
27.2 System Overview ...............................................................................................338
27.3 Data Registers ...................................................................................................338
27.4 Boundary-scan Specific JTAG Instructions .......................................................340
27.5 Boundary-scan Related Register in I/O Memory ...............................................341
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