AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 35
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AT90USB647-MU
Manufacturer Part Number
AT90USB647-MU
Description
MCU, 8BIT, 64K FLASH, USB, 64QFN
Manufacturer
Atmel
Specifications of AT90USB647-MU
Controller Family/series
AT90
No. Of I/o's
48
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
16MHz
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
64KB
Oscillator Type
External, Internal
Package
64QFN EP
Device Core
AVR
Family Name
AT90
Maximum Speed
20 MHz
Ram Size
4 KB
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
48
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
Lead Free Status / Rohs Status
Details
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5.5.7
7593K–AVR–11/09
External Memory Control Register B – XMCRB
Table 5-4.
• Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-
nal memory address space, see
• Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-
nal memory address space, see
Table 5-5.
Note:
• Bit 7– XMBK: External Memory Bus-keeper Enable
Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is
enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-
stated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE,
Bit
Read/Write
Initial Value
SRWn1
SRL2
0
0
1
1
0
0
0
1
1
1
1
1. n = 0 or 1 (lower/upper sector).
SRWn0
For further details of the timing and wait-states of the External Memory Interface, see Figures
5-6 through Figures 5-9 for how the setting of the SRW bits affects the timing.
7
XMBK
R/W
0
0
1
0
1
Sector limits with different settings of SRL2..0
Wait States
SRL1
0
1
1
0
0
1
1
R
6
–
0
Wait States
No wait-states
Wait one cycle during read/write strobe
Wait two cycles during read/write strobe
Wait two cycles during read/write and wait one cycle before driving out
new address
(1)
SRL0
5
–
R
0
x
0
1
0
1
0
1
Table
Table
4
–
R
0
Sector Limits
Lower sector = N/A
Upper sector = 0x2100 - 0xFFFF
Lower sector = 0x2100 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
Lower sector = 0x2100 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
Lower sector = 0x2100 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
Lower sector = 0x2100 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
Lower sector = 0x2100 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
Lower sector = 0x2100 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
5-5.
5-5.
3
–
R
0
2
XMM2
R/W
0
1
XMM1
R/W
0
AT90USB64/128
0
XMM0
R/W
0
XMCRB
35
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